19.6 A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode

Bol, David; Schramme, Maxime; Moreau, Ludovic; Haine, Thomas; Xu, Pengcheng; Frenkel, Charlotte; Dekimpe, Rémi; Stas, François; Flandre, Denis

doi:10.1109/isscc.2019.8662293

Cited by 10 publications

(10 citation statements)

References 2 publications

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“…To give an idea of how Freezer would fit in a low-end IoT node, we can compare it with a ultra-low-power, sizeoptimised SoC, implemented with the same 28nm FDSOI technology node such as the one presented in [25]. In terms of area the SoC is 0.7mm 2 , while its power consumption is 3µW/MHz giving at 48MHz a power consumption of 144µW.…”

Section: F Energy and Area Overhead Considerationsmentioning

confidence: 99%

Freezer: A Specialized NVM Backup Controller for Intermittently-Powered Systems

Pala,

Miro-Panades,

Sentieys

2021

Preprint

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The explosion of IoT and wearable devices determined a rising attention towards energy harvesting as source for powering these systems. In this context, many applications cannot afford the presence of a battery because of size, weight and cost issues. Therefore, due to the intermittent nature of ambient energy sources, these systems must be able to save and restore their state, in order to guarantee progress across power interruptions. In this work, we propose a specialized backup/restore controller that dynamically tracks the memory accesses during the execution of the program. The controller then commits the changes to a snapshot in a Non-Volatile Memory (NVM) when a power failure is detected. Our approach does not require complex hybrid memories and can be implemented with standard components. Results on a set of benchmarks show an average 8× reduction in backup size. Thanks to our dedicated controller, the backup time is further reduced by more than 100×, with an area and power overhead of only 0.4% and 0.8%, respectively, w.r.t. a low-end IoT node.

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Section: F Energy and Area Overhead Considerationsmentioning

confidence: 99%

Freezer: A Specialized NVM Backup Controller for Intermittently-Powered Systems

Pala,

Miro-Panades,

Sentieys

2021

Preprint

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“…To interface with a large variety of external devices, these systems offer a wide set of peripherals such as I2C, UART, SPI, and GPIOs. SoAs energy-efficient MCUs optimized for ultra-low-power (3µW/MHz) [12] and performance (938 MHz) [33] have been implemented in FDSOI technology leveraging body-biasing to compensate processvoltage-temperature (PVT) variations, and to control performance and power to achieve higher energy efficiency.…”

Section: Mcusmentioning

confidence: 99%

“…Single Core [12], [31], [32], [33] Low Power [34], [35] StandAlone [36], [37], [38], [39] SW Accelerator [9], [40] Low Power SoC [41] MCU SoC [28], [29], [30], HW Accelerator [13], [42] HP [43], [44] This Work HW/SW Accelerator [45], [46] HP SoC [47], [48] HP SoC [49] application processors (usually ARM-based embedded processors such as the Xilinx Zynq-7000 SoC [47] and Intel Arria V SoC [48], in the case of Microsemi PolarFire [56] RISC-V processors). As a result, high-end FPGAs have typical power consumption in the order of tens of Watts [57], and they are usually used as high-performance accelerators on servers connected via Ethernet or PCI interfaces [58].…”

Section: Mcu Fpga Efpgamentioning

confidence: 99%

“…SoA MCUs can offer competitive Power-Performance-Area (PPA) figures by leveraging parallel Near-Threshold Computing (NTC) [7], and advanced low-power technologies such as Fully Depleted Silicon-On-Insulator (FDSOI) coupled with performance-power management techniques such as bodybias [8] and power-saving states [9]. As it has been shown in [9], [10], [11], [12], these techniques make possible the use of MCUs on edge computing devices, meeting PPA constraints for a wide range of applications in the IoT domain, yet providing high versatility. To increase performance, MCUs are often customized with on-chip full-custom accelerators that speed up the execution of part of the applications as for example neural-networks [13], frequency-domain-transforms [14], linear algebra [15], security engines [16].…”

Section: Introductionmentioning

confidence: 99%

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Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes

Schiavone¹,

Rossi²,

Mauro³

et al. 2020

Preprint

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A wide range of Internet of Things (IoT) applications require powerful, energy-efficient and flexible end-nodes to acquire data from multiple sources, process and distill the sensed data through near-sensor data analytics algorithms, and transmit it wirelessly. This work presents Arnold: a 0.5 V to 0.8 V, 46.83 µW/MHz, 600 MOPS fully programmable RISC-V Microcontroller unit (MCU) fabricated in 22 nm Globalfoundries GF22FDX (GF22FDX) technology, coupled with a stateof-the-art (SoA) microcontroller to an embedded Field Programmable Gate Array (FPGA). We demonstrate the flexibility of the System-On-Chip (SoC) to tackle the challenges of many emerging IoT applications, such as (i) interfacing sensors and accelerators with non-standard interfaces, (ii) performing on-the-fly pre-processing tasks on data streamed from peripherals, and (iii) accelerating near-sensor analytics, encryption, and machine learning tasks. A unique feature of the proposed SoC is the exploitation of body-biasing to reduce leakage power of the embedded FPGA (eFPGA) fabric by up to 18× at 0.5 V, achieving SoA state bitstream-retentive sleep power for the eFPGA fabric, as low as 20.5 µW. The proposed SoC provides 3.4× better performance and 2.9× better energy efficiency than other fabricated heterogeneous re-configurable SoCs of the same class.

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“…The ultra-thin body and buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS platform is an outstanding platform for cryo-CMOS, thanks to its very low power consumption feature, large integration and very good analog and radiofrequency (RF) performances [13], [14], as required for qubit write and read operations. Furthermore, the back-gate bias is a useful knob in its ability to tune the power consumption, and adjust for process or temperature variations [15]. 28-nm FD-SOI CMOS is also a viable solution for quantumintegrated circuits as the implementation of qubits is compatible with this platform and just additionally requires a few nonstandard process steps, like e-beam lithography [10], [11].…”

Section: Introductionmentioning

confidence: 99%

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K

Nyssens

Halder

Esfeh

et al. 2020

IEEE J. Electron Devices Soc.

Self Cite

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This work presents a detailed RF characterization of 28-nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e. current-gain cutoff frequency (ft) and maximum oscillation frequency (fmax), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ~130 GHz in ft and ~75 GHz in fmax is observed for the shortest device (25 nm) at low temperature. The behavior of RF FoMs versus temperature is discussed in terms of small-signal equivalent circuit elements, both intrinsic and extrinsic (parasitics). This study suggests 28-nm FD-SOI nMOSFETs as a good candidate for future cryogenic applications down to 4.2 K and clarifies the origin and limitations of the performance.

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19.6 A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode

Cited by 10 publications

References 2 publications

Freezer: A Specialized NVM Backup Controller for Intermittently-Powered Systems

Freezer: A Specialized NVM Backup Controller for Intermittently-Powered Systems

Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes

28-nm FD-SOI CMOS RF Figures of Merit Down to 4.2 K

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