1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing

Lopez, J. Minguet; Rummens, François; Reganaz, Lucas; Heraud, A.; Hirtzlin, Tifenn; Grenouillet, L.; Navarro, G.; Bernard, M.; Carabasse, C.; Castellani, N.; Meli, V.; Magis, T.; Vianello, Elisa; Sabbione, C.; Deleruyelle, Damien; Bocquet, Marc; Portal, J.M.; Molas, G.; Andrieu, F.

doi:10.1109/imw52921.2022.9779253

Cited by 6 publications

(12 citation statements)

References 2 publications

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“…In addition, to compare the performance of the n-SIMPLY and hybrid BNN accelerators, the performance and characteristics of RRAM-based BNN inference accelerators from the literature [6,8,42,46,47,50,51] accelerate in the analog domain the BNN VMM. However, each work uses different arrays sizes, topologies, devices, and technologies, thus complicating the comparison between different accelerators.…”

Section: Tablementioning

confidence: 99%

“…Specifically, in [8,47] the TOPS/ W metric is reported, however this metric indicates the maximum performance that can be achieved in specific conditions, which are not necessarily the one achieved by the circuit in a generic inference task. Still, some works [42,[50][51][52] directly report the performance, or sufficient data that can be used to estimate the performance of their accelerator on an MNIST handwritten digits classification task. Among these works, the results reported by Yu et al in [42,52] show the worst performance, however their solution was optimized for training directly on chip the entire network parameters, thus introducing additional overheads.…”

Section: Tablementioning

confidence: 99%

“…Compared with the results reported by Minguet et al in [50], the n-SIMPLY Binary Tree Adder implementation achieves similar EDP performance while the Hybrid implementation can further reduce the EDP. The lowest energy consumption for an MNIST inference task, was estimated from the work of Lopez et al [51], where the authors proposed a subthreshold read scheme in which 1S1R devices are read using a read voltage that is lower than the threshold voltage of the selector device, achieving a read energy of 76 fJ/bit.…”

Section: Tablementioning

confidence: 99%

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Study of RRAM-Based Binarized Neural Networks Inference Accelerators Using an RRAM Physics-Based Compact Model

Zanotti¹,

Pavan²,

Puglisi³

2023

Artificial Intelligence

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In-memory computing hardware accelerators for binarized neural networks based on resistive RAM (RRAM) memory technologies represent a promising solution for enabling the execution of deep neural network algorithms on resource-constrained devices at the edge of the network. However, the intrinsic stochasticity and nonidealities of RRAM devices can easily lead to unreliable circuit operations if not appropriately considered during the design phase. In this chapter, analysis and design methodologies enabled by RRAM physics-based compact models of LIM and mixed-signal BNN inference accelerators are discussed. As a use case example, the UNIMORE RRAM physics-based compact model calibrated on an RRAM technology from the literature, is used to determine the performance vs. reliability trade-offs of different in-memory computing accelerators: i) a logic-in-memory accelerator based on the material implication logic, ii) a mixed-signal BNN accelerator, and iii) a hybrid accelerator enabling both computing paradigms on the same array. Finally, the performance of the three accelerators on a BNN inference task is compared and benchmarked with the state of the art.

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Section: Tablementioning

confidence: 99%

Section: Tablementioning

confidence: 99%

Section: Tablementioning

confidence: 99%

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Study of RRAM-Based Binarized Neural Networks Inference Accelerators Using an RRAM Physics-Based Compact Model

Zanotti¹,

Pavan²,

Puglisi³

2023

Artificial Intelligence

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“…Nevertheless, 1S1R stack adjustments and optimized programming patterns as well as OTS material engineering are paths of improvement to enhance endurance for more cycling demanding applications. [22,23] In this context, the OxRAM resistive state can be read by applying a certain reading voltage (V read ) caught between V th-HRS and V th-LRS . If the OxRAM is in LRS, the OTS switching occurs, and I LRS is read.…”

Section: S1r Programming and Reading Operationmentioning

confidence: 99%

“…OTS co-integration with HfO 2 -based OxRAM has been satisfactorily demonstrated in the previous years. [18,[20][21][22][23] Through stack design and applied programming conditions adaptation, the 1S1R dynamic switching capabilities have been elucidated, the 1S1R binarized window margin optimized, and its programming endurance capabilities enlarged. [22] In particular, the 1S1R pertinence for standard low-precision synaptic weight encoding during network training on-chip has been demonstrated.…”

Section: Introductionmentioning

confidence: 99%

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

Lopez

Rafhay

Dampfhoffer

et al. 2022

Adv Elect Materials

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in graphics processing units (GPUs) or central processing units (CPU) remains extremely challenging. On the contrary, the brain promises very high cognitive capacity while preserving exceptional energy efficiency. One of the main differences between GPUs or CPUs and the brain is memory management. On the one hand, a physical separation exists in GPUs and CPUs between arithmetic and storage units, which is at the origin of enormous energy consumption associated with data transfer between both units. [1] This trend is particularly exacerbated for Artificial Neural Networks (ANNs), which require a very large amount of memory access. On the other hand, the biological neurons and synapses are close to each other in the brain. Accordingly, developing non-von-Neumann architectures to perform in or near-memory computing with non-volatile memory (NVM) technologies is one of the most promising strategies to improve the energetic efficiency of artificial intelligence. [2] Another relevant difference between artificial processors and the brain is the way information is coded. On the one hand, GPUs and CPUs rely on high-precision floating-point outputs. On the other hand, binarized sparse and asynchronous spikes are used to communicate in the brain. In particular, a neuron receives through Single memristor crossbar arrays are a very promising approach to reduce the power consumption of deep learning accelerators. In parallel, the emerging bio-inspired spiking neural networks (SNNs) offer very low power consumption with satisfactory performance on complex artificial intelligence tasks. In such neural networks, synaptic weights can be stored in nonvolatile memories. The latter are massively read during inference, which can lead to device failure. In this context, a 1S1R ( 1Selector 1 Resistor) device composed of a HfO 2 -based OxRAM memory stacked on a Ge-Se-Sb-N-based ovonic threshold switch (OTS) back-end selector is proposed for high-density binarized SNNs (BSNNs) synaptic weight hardware implementation. An extensive experimental statistical study combined with a novel Monte Carlo model allows to deeply analyze the OTS switching dynamics based on field-driven stochastic nucleation of conductive dots in the layer. This allows quantifying the occurrence frequency of OTS erratic switching as a function of the applied voltages and 1S1R reading frequency. The associated 1S1R reading error rate is calculated. Focusing on the standard machine learning MNIST image recognition task, BSNN figures of merit (footprint, electrical consumption during inference, frequency of inference, accuracy, and tolerance to errors) are optimized by engineering the network topology, training procedure, and activations sparsity.

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Ternary Łukasiewicz logic using memristive devices

Bengel,

Liu,

Chen

et al. 2023

Neuromorph. Comput. Eng.

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Memristive devices based on the Valence Change Mechanism (VCM) are promising devices for storage class memory, neuromorphic computing and logic-in memory (LIM) applications. They are suited for such a wide range of applications, due to their possibility for extreme dense integration, low power consumption and multilevel capabilities. Through LIM concepts, Boolean logic operations can be performed directly in memory. In many of these concepts, the resistance state of the device is interpreted as the logical input and output of the logic function, which is why these concepts are called 'stateful' logic. Most of the proposed ideas, however, are defined based on only binary switching VCM devices and neglect their multi-level capabilities. Extending LIM concepts towards multinary logic, e.g. a ternary logic, would increase the data density inside the memory array and reduce the number of devices required to perform a certain operation. In this work, we discuss two possibilities of realising a ternary logic based on the analog switching in the RESET or in the SET direction. For both directions we verify the logic functionality by showing the basic operations of IMPLY, Negation and FALSE operation, which together form a functionally complete logic. Additionally, for both switching directions, we discuss a 41-Trit (≈ 64-Bit) addition. For all investigations the physics-based compact model JART VCM v1b is used, which has been verified on the RESET direction multilevel properties of the TaOx devices.

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1S1R sub-threshold operation in Crossbar arrays for low power BNN inference computing

Cited by 6 publications

References 2 publications

Study of RRAM-Based Binarized Neural Networks Inference Accelerators Using an RRAM Physics-Based Compact Model

Study of RRAM-Based Binarized Neural Networks Inference Accelerators Using an RRAM Physics-Based Compact Model

1S1R Optimization for High‐Frequency Inference on Binarized Spiking Neural Networks

Ternary Łukasiewicz logic using memristive devices

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