2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters

Vivet, Pascal; Guthmuller, Èric; Thonnart, Yvain; Pillonnet, Gaël; Moritz, Guillaume; Miro-Panades, Ivan; Fuguet, César; Durupt, Jean; Bernard, Christian; Varreau, D.; Pontes, Julian; Thuries, Sébastien; Coriat, David; Harrand, Michel; Dutoit, Denis; Lattard, Didier; Arnaud, L.; Charbonnier, Jean; Coudrain, P.; Garnier, A.; Berger, Frédéric; Gueugnot, Alain; Greiner, Alain; Meunier, Quentin; Farcy, A.; Arriordaz, Alexandre; Chéramy, S.; Clermidy, Fabien

doi:10.1109/isscc19947.2020.9062927

Cited by 49 publications

(18 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, even higher losses in the PDN and the metal layers would be expected in case of higher-integrated, e.g., 7 nm, CMOS nodes [30]. Accordingly, future research will also focus on alternative solutions that do not require a direct integration of the PMIC on the CPU die, e.g., 3D realizations using chiplets [31], which extends the current design space with respect to system complexity, efficiency, and costs.…”

Section: Discussionmentioning

confidence: 99%

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Bezerra

Krismer

Kolar

et al. 2020

IEEE Open J. Power Electron.

View full text Add to dashboard Cite

Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB-and inductorbased four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1 % at an output power of Pout = 640 mW and a switching frequency of fs = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at fs = 50 MHz and Pout ∈ [500 mW, 600 mW]; at Pout = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

show abstract

Section: Discussionmentioning

confidence: 99%

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Bezerra

Krismer

Kolar

et al. 2020

IEEE Open J. Power Electron.

View full text Add to dashboard Cite

show abstract

“…2.5D integration, also known as the interposer technology, facilitates system-level integration of 2D chips sideby-side. An interposer serves as an integration carrier and accommodates an underlying system-level interconnect fabric to provide inter-chip communication [18], [19], [20], [21], thereby resembling a modern version of a printed circuit board. Building an advanced electronic system using an interposer is considered less complex than native 3D integration [18], [19].…”

Section: 5d and 3d Integrationmentioning

confidence: 99%

“…Regarding manufacturing and integration cost, we note that both sides have been argued for, i.e., interposers are cheaper than 3D ICs [18] versus interposers are more costly [26]. However, once system-level cost are considered, the interposer technology remains promising, also because active interposers improve testability [20], [24], [25] and, thereby, allow to better manage yield of the final system.…”

Section: 5d and 3d Integrationmentioning

confidence: 99%

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Nabeel¹,

Ashraf²,

Patnaik

et al. 2020

IEEE Trans. Comput.

View full text Add to dashboard Cite

Dedicated, after acceptance and publication, in memory of the late Vassos Soteriou. For the first time, we leverage the 2.5D interposer technology to establish system-level security in the face of hardware-and software-centric adversaries. More specifically, we integrate chiplets (i.e., third-party hard intellectual property of complex functionality, like microprocessors) using a security-enforcing interposer. Such hardware organization provides a robust 2.5D root of trust for trustworthy, yet powerful and flexible, computation systems. The security paradigms for our scheme, employed firmly by design and construction, are: 1) stringent physical separation of trusted from untrusted components, and 2) runtime monitoring. The system-level activities of all untrusted commodity chiplets are checked continuously against security policies via physically separated security features. Aside from the security promises, the good economics of outsourced supply chains are still maintained; the system vendor is free to procure chiplets from the open market, while only producing the interposer and assembling the 2.5D system oneself. We showcase our scheme using the Cortex-M0 core and the AHB-Lite bus by ARM, building a secure 64-core system with shared memories. We evaluate our scheme through hardware simulation, considering different threat scenarios. Finally, we devise a physical-design flow for 2.5D systems, based on commercial-grade design tools, to demonstrate and evaluate our 2.5D root of trust.

show abstract

“…Voltage Regulators (VRs) are used for power management of modern 3D-ICs, providing voltage levels that are different than the standard printed circuit board (PCB) supply. Integrated VRs also enable fast voltage scaling to improve core performance while maintaining acceptable power consumption and voltage-drop levels [11]. In addition, VRs allow to decouple power supply from logic circuits and keep constant voltage levels in case of supply noise and transient load changes.…”

Section: Background and Related Workmentioning

confidence: 99%

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

Najibi

Hunter

Levisse

et al. 2020

2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

View full text Add to dashboard Cite

Flow cell arrays (FCAs) provide efficient on-chip liquid cooling and electrochemical power generation capabilities in three-dimensional multi-processor systems-on-chip (3D MPSoCs). When connected to power delivery networks (PDNs) of chips, the current flowing between FCA electrodes partially supplies logic gates and compensates over 20% V dd drop in highperformance 3D systems. However, operation voltages of CMOS technologies are generally higher than the voltage corresponding to the maximal FCA power generation. Hence, directly connecting FCAs to 3D MPSoC power grids results in sub-optimal performance. In this paper, we design an on-chip direct current to direct current (DC-DC) converter to improve FCA power generation in high-performance 3D MPSoCs. We use switched capacitor (SC) technology and explore different design space parameters to achieve minimal area requirement and maximal power extraction. The proposed converter enables a stable and optimal voltage between FCA electrodes. Furthermore, it allows us to dynamically control FCA connectivity to 3D PDNs, and switch off power extraction during chip inactivity. We show that regulated FCAs generate up to 123% higher power with respect to the case they are directly connected to 3D PDNs. In addition, connecting multiple flow cells to a single optimized converter reduces area requirement down to 1.26%, while maintaining IRdrop below 5%. Finally, we show that activity-based dynamic FCA switching extends by over 1.8× and 4.5× electrolytes lifetime for a processor duty-cycle of 50% and 20%, respectively. Index Terms-3D MPSoCs, FCA technology, on-chip power generation, 3D power delivery networks, DC-DC converter.

show abstract

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm² Inter-Chiplet Interconnects and 156mW/mm²@ 82%-Peak-Efficiency DC-DC Converters

Cited by 49 publications

References 5 publications

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

Contact Info

Product

Resources

About

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters

Cited by 49 publications

References 5 publications

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters

Contact Info

Product

Resources

About

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm² Inter-Chiplet Interconnects and 156mW/mm²@ 82%-Peak-Efficiency DC-DC Converters