2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

Lee, Changhyun; Park, Changkun

doi:10.1155/2014/967181

Cited by 5 publications

(9 citation statements)

References 33 publications

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“…Lee and Park (2014) proposed a modified mode-locking differential cascode PA to minimize the time delay, as shown in Figure 12 [42]. This design was focused on improving the high power gain.…”

Section: Differential Cascode Architecturementioning

confidence: 99%

“…The measured power-added efficiency for the proposed design was 34.9%, whereas the saturated output power was 23.32 dBm. Lee and Park (2014) proposed a modified mode-locking differential cascode PA to minimize the time delay, as shown in Figure 12 [42]. This design was focused on improving the high power gain.…”

Section: Differential Cascode Architecturementioning

confidence: 99%

“…The transconductance of the transistors was increased by the cross-coupling capacitor technique [44,45]. Consequently, the power gain increased because it was proportional to Lee and Park (2014) proposed a modified mode-locking differential cascode PA to minimize the time delay, as shown in Figure 12 [42]. This design was focused on improving the high power gain.…”

Section: Differential Cascode Architecturementioning

confidence: 99%

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Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

et al. 2019

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Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

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Section: Differential Cascode Architecturementioning

confidence: 99%

Section: Differential Cascode Architecturementioning

confidence: 99%

Section: Differential Cascode Architecturementioning

confidence: 99%

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Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

et al. 2019

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“…Alternatively, M SW can be removed from the power amplifier, as shown in Figure (b), if the V G,CG value of M CG,1 and M CG,2 is used to control the operation of the power amplifier. However, the output power of the power amplifiers shown in Figure (b) cannot be controlled through the input power, as is normally done in a linear amplifier [8–11].…”

Section: Typical Mode‐locking Techniquementioning

confidence: 99%

“…If the gain of the power amplifier is low, an additional driver stage is required to obtain sufficient gain, and hence the overall efficiency of the power amplifier is degraded. Among the various efficiency‐ and gain‐enhancement techniques, we investigate the mode‐locking technique, which is often applied to switching‐mode amplifiers . In general, given that the mode‐locking technique utilizes the unstable properties of a cross‐coupled structure in a differential amplifier, stability problems should first be solved for linear amplifier applications.…”

Section: Introductionmentioning

confidence: 99%

A 2.4‐GHz CMOS power amplifier using a gain and stability enhancement technique for IEEE 802.11N WLAN applications

Lee

Park

2016

Micro & Optical Tech Letters

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In this work, we propose a gain and stability enhancement technique with compact size for RF CMOS linear power amplifier applications. The proposed amplifier is designed with differential and cascode structures. To realize a compact size of the power amplifier, the driver stage is merged into the power stage of the power amplifier. To minimize the number of essentially required inductors, the load impedance of the power stage is shared with the driver stage of the power amplifier. Additionally, to moderate stability problems in the power amplifier, the closed loop is removed using a common‐gate transistor, which operates in the saturation region. The power amplifier can then operate in the linear operation. To prove the feasibility of the proposed linear amplifier, we designed a 2.4 GHz CMOS power amplifier using the 180‐nm RF CMOS process. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2265–2268, 2016

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Conversion Economics of Forest Biomaterials: Risk and Financial Analysis of CNC Manufacturing

Assis

Houtman

Phillips

et al. 2017

Biofuels Bioprod Bioref

111

125

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Commercialization of cellulose nanocrystals (CNC) presents opportunities for a wide range of new products. Techno‐economic assessments can provide insightful information for the efficient design of conversion processes, drive cost‐saving efforts, and reduce financial risks. In this study, we conducted techno‐economic assessments for CNC production using information from the USDA Forest Products Laboratory Pilot Plant, literature, and discussions with experts. Scenarios considered included variations related to greenfield, co‐location, and acid recovery. Operating costs, capital investment, minimum product selling price (MPSP), financial performance metrics, and the effect of drying and higher reaction yields on CNC manufacturing financials were estimated for each scenario. The lowest MPSP was found for the co‐location without acid recovery scenario, mainly driven by capital investment. Risk analysis indicates 95% probability of manufacturing costs lower than USD 5900/t of CNC (dry equivalent) and a MPSP lower than USD 7200/t of CNC (dry equivalent). Finally, based on our analysis, we provide guidance on process optimizations that can improve the economic performance of CNC manufacturing process. In addition, a risk profile of the CNC manufacturing business is provided. © 2017 Society of Chemical Industry and John Wiley & Sons, Ltd

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2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

Cited by 5 publications

References 33 publications

Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

A 2.4‐GHz CMOS power amplifier using a gain and stability enhancement technique for IEEE 802.11N WLAN applications

Conversion Economics of Forest Biomaterials: Risk and Financial Analysis of CNC Manufacturing

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