2.4-GHz Complementary Metal Oxide Semiconductor Power Amplifier Using High-Quality Factor Wafer-Level Bondwire Spiral Inductor

Lin, Kaiqi; Chiou, Hwann-Kaeo; Wu, Po-Chang; Chen, Wei-Hsien; Ko, Chun-Lin; Juang, Ying‐Zong

doi:10.1109/tcpmt.2012.2227260

Cited by 15 publications

(15 citation statements)

References 35 publications

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“…These dimensions of spiral inductors are listed in Table 2. The formula that is valid for planar spiral integrated inductors can be defined as [8]:…”

Section: Stand-alone Inductor Structurementioning

confidence: 99%

Chip-Package Co-Design for Optimization of 5.8 GHZ Lna Performance Based on Embedded Inductors

Sun¹,

Sun²,

Sun³

et al. 2018

PIER M

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This paper presents the design and demonstration of an optimized land grid array (LGA) structure for low noise amplifier (LNA). In order to achieve better circuit performance, the novel chippackage co-design method based on embedded inductors is used. The optimized structure is accurately modeled by ANSYS software. S-parameter is utilized to help in understanding the contributing to the optimized LGA structure. The simulation results for the novel LNA co-design structure show the gain 14.35 dB (> 10 dB), input reflection coefficient −15.63 dB (< −10 dB), output reflection coefficient −24.43 dB (< −10 dB), reverse-isolation −44.7 dB (< −20 dB), and noise figure 2.99 dB (< 4 dB), and indicate that the optimized LGA structure based on embedded inductors is fully capable of supporting 5.8 GHz LNA application. 1. INTRODUCTION With the continuous development of information technology, the demand for low cost and high performance communication systems is increasing. In most RF circuit blocks, low noise amplifiers are usually designed as a single-port circuit for connecting with the band-pass filter or antenna [1, 2]. In order to achieve an efficient input power matching, many on-chip inductors are used in LNA design. These on-chip inductors, implemented in Complementary Metal Oxide Semiconductor transistor (CMOS) technology, not only consume high silicon area, but also have poor electrical performances [3], such as low quality factors. On the other hand, as the operating frequency or bandwidth increases for high data rate, the LNAs become more susceptible to package effects. Those package parasitic effects will cause significant degradation in gain and impedance of LNAs [4]. In previous works, the conventional ceramic quad flat no-lead (QFN) package is usually used for LNA design to satisfy highperformance [5, 6]. The low-pass filter models are used for wire bond packaged LNAs to reveal the package input/output interconnect behave and like an impedance transformer in altering the matching network for optimization design. In this paper, a chip-package co-design of 5.8 GHz cascade common-source LNA based on embedded inductors is presented. In view of electrical performance design, the matching networks on the package substrate by using embedded inductor are constructed. Designing embedded inductor elements can reduce the number of passive elements and achieve special matching values. In Section 2, a special cascade common-source LNA chip with an on-chip matching network and its performance is discussed in detail. Then, the embedded inductor on the LGA substrate is built and analyzed in Section 3. By taking advantage of the packaging parasitic of bond wire, the LNA co-design architecture is established and optimized in Sections 4-5. Finally, a brief conclusion is given in Section 6.

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“…These dimensions of spiral inductors are listed in Table 2. The formula that is valid for planar spiral integrated inductors can be defined as [8]:…”

Section: Stand-alone Inductor Structurementioning

confidence: 99%

Chip-Package Co-Design for Optimization of 5.8 GHZ Lna Performance Based on Embedded Inductors

Sun¹,

Sun²,

Sun³

et al. 2018

PIER M

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“…The wide metal track in the standard CMOS process must comply with the slot rules of the design rule check, reducing the quality factor (Q) of the inductors and increasing the power loss. In contrast, the bondwire can support a high drain current with high Q. Lin et al [26] proposed a PA that uses a wafer-level bondwire spiral inductor (BSL) with a high Q. Comparisons of Qbetween a conventional CMOS standard spiral inductor (SSL) and a wafer-level BSL revealed that, at the same inductance, the Q is 30 for a BSL, but 10 for an on-chip SSL.…”

Section: -Ghz Pa With Linearisermentioning

confidence: 99%

Compact high‐linearity, high‐efficiency complementary metal–oxide–semiconductor power amplifier with post‐distortion lineariser for wireless local area network and Wireless Gigabit Alliance applications

Lin¹,

Chiou

Ko³

et al. 2016

IET Microwaves, Antennas & Propagation

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This study proposes a post‐distortion linearisation technique for 5 and 60 GHz complementary metal–oxide–semiconductor (CMOS) power amplifiers (PAs). The technique improves the output 1 dB gain compression point (OP1dB) and power‐added efficiency (PAE) of the PA when the lineariser is turned on. The 5 GHz PA that is fabricated in tsmcTM 0.18 μm CMOS achieves a 16.3 dB gain, a 20 dBm OP1dB and a 32.6% PAE. The linearised 5 GHz PA improves the OP1dB and PAE by 2.3 dB and 3.2% as compared to the PA without lineariser. The difference between the OP1dB and saturated power (Psat) is <0.2 dB. The 60 GHz PA was implemented in a 90 nm CMOS process with a chip area of 0.57 mm2. The PA achieves a 14.8 dB gain, a 16.8 dBm OP1dB with a 16.3% PAE and a 15 GHz 3 dB bandwidth. The power difference between the OP1dB and Psat is <0.3 dB. The linearised 60 GHz PA improves the OP1dB and PAE by 3.2 dB and 5.8% as compared to the PA without lineariser.

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“…We propose a high-Q and wide tunable bondwire inductor (TBI) digitally controlled by RF CMOS switches. The bondwire inductors are adopted because their self-resistance and standard manufacturing process cost are much lower than those of spiral inductors [16,17]. The RF switches are designed using 180 nm silicon-on-insulator (SOI) CMOS technology to minimize their turn-on resistance.…”

Section: Introductionmentioning

confidence: 99%

Digitally-Controlled Bondwire Inductor with High Quality Factor and Wide Tuning Range

Lee

2020

J Electromagn Eng Sci

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A tunable bondwire inductor (TBI) with high-quality factor and wide tuning range is presented. The proposed TBI is fabricated on a single chip by combining a single-pole four-throw (SP4T) switch integrated circuit (IC) and four bondwire inductors on a package substrate. The SP4T switch IC is fabricated using 180 nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The fabricated TBI chip exhibits a 521% tuning range of inductance from 1.77 to 11 nH at 0.1 GHz and a relatively high-quality factor. To the knowledge of the authors, the results of this work demonstrate the best combined performance of inductance tuning range and quality factor.

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2.4-GHz Complementary Metal Oxide Semiconductor Power Amplifier Using High-Quality Factor Wafer-Level Bondwire Spiral Inductor

Cited by 15 publications

References 35 publications

Chip-Package Co-Design for Optimization of 5.8 GHZ Lna Performance Based on Embedded Inductors

Chip-Package Co-Design for Optimization of 5.8 GHZ Lna Performance Based on Embedded Inductors

Compact high‐linearity, high‐efficiency complementary metal–oxide–semiconductor power amplifier with post‐distortion lineariser for wireless local area network and Wireless Gigabit Alliance applications

Digitally-Controlled Bondwire Inductor with High Quality Factor and Wide Tuning Range

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