Compact high‐linearity, high‐efficiency complementary metal–oxide–semiconductor power amplifier with post‐distortion lineariser for wireless local area network and Wireless Gigabit Alliance applications

Abstract

This study proposes a post‐distortion linearisation technique for 5 and 60 GHz complementary metal–oxide–semiconductor (CMOS) power amplifiers (PAs). The technique improves the output 1 dB gain compression point (OP1dB) and power‐added efficiency (PAE) of the PA when the lineariser is turned on. The 5 GHz PA that is fabricated in tsmcTM 0.18 μm CMOS achieves a 16.3 dB gain, a 20 dBm OP1dB and a 32.6% PAE. The linearised 5 GHz PA improves the OP1dB and PAE by 2.3 dB and 3.2% as compared to the PA without lineariser. The difference between the OP1dB and saturated power (Psat) is <0.2 dB. The 60 GHz PA was implemented in a 90 nm CMOS process with a chip area of 0.57 mm2. The PA achieves a 14.8 dB gain, a 16.8 dBm OP1dB with a 16.3% PAE and a 15 GHz 3 dB bandwidth. The power difference between the OP1dB and Psat is <0.3 dB. The linearised 60 GHz PA improves the OP1dB and PAE by 3.2 dB and 5.8% as compared to the PA without lineariser.

A 0.8 mm2 Sub-GHz GaAs HBT Power Amplifier for 5G Application Achieving 57.5% PAE and 28.5 dBm Maximum Linear Output Power

“…Efficiency and linearity using CMOS process is inferior due to the higher substrate losses and low breakdown voltage [31]. Among the critical component is the inductor where high quality on-chip inductors are preferred for high frequency operation for RFIC solution in CMOS [32], [33]. An un-even bias scheme, which consists of a programmable gain amplifier biased at Class C and a power stage biased at Class AB is able to improve the efficiency and linearity of the CMOS PA in low power operating region [34].…”