2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs

Horst, Fabian; Farokhnejad, Atieh; Zhao, Qing‐Tai; Iñı́guez, Benjamı́n; Kloes, Alexander

doi:10.1109/ted.2018.2856891

Cited by 32 publications

(9 citation statements)

References 14 publications

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“…This facilitates electron tunneling from the source valence band to the channel conduction band. [4][5][6][7][8][9][10][11][12] This suggests that there is an inherent relationship between the threshold voltage of a TFET and its tunneling width. For a TFET, the threshold voltage will always correspond to a unique value of the tunneling width.…”

Section: Modeling: Algorithm and Methodologymentioning

confidence: 99%

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Model for Predicting the Threshold Voltage of Tunnel Field-Effect Transistors Using Linear Regression

Kumar

Parida

Goswami

et al. 2021

J. Electron. Mater.

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A linear regression-based method for extracting the threshold voltage of tunnel field-effect transistors (TFETs) is presented. The minimum tunneling width at the threshold voltage of a TFET is expressed as a linear function of tunneling widths corresponding to gate voltages. The regression is carried out using known simulated TFETs and verified on unknown TFETs, achieving an R 2 value of 96.50%. The model is compared with and verified against methods and devices reported in literature, confirming that it is effective for predicting the threshold voltage.

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Section: Modeling: Algorithm and Methodologymentioning

confidence: 99%

“…The scope of such analytical models has also increased in recent times as they help to describe the operation of devices but with a greater emphasis on the physics of their operation. Various analytical models have been proposed for TFETs, 9,10 and ongoing attempts are being made to model the various electrical parameters of TFETs.…”

Section: Introductionmentioning

confidence: 99%

Model for Predicting the Threshold Voltage of Tunnel Field-Effect Transistors Using Linear Regression

Kumar

Parida

Goswami

et al. 2021

J. Electron. Mater.

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“…First, we describe the different topologies, the 32 nm iPDK, and, above all, the TFET physics-based models for circuit simulations [20,21]. For the latter, we have included a physics approach that considers the parasitic components [22] for a fair comparison for the post-layout simulation results. Then, the topologies are optimized using the same method from our previous work [13], and the simulations are carried out using the circuit TCAD simulator Synopsys.…”

Section: Introductionmentioning

confidence: 99%

From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

et al. 2022

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In this present work, different Cross-Coupled Differential Drive (CCDD) CMOS bridge rectifiers are designed using either 32 nm or Tunnel-FET (TFET) technology. Commercial PDK has been used for the 32 nm technology, while lookup tables (LUT) resulting from a physics model have been applied for the TFET. To consider the parasitic effects for the circuit performances, the 32 nm-based circuits have been laid out, while a parasitic model has been included in the TFET LUT for circuit implementation. In this work, the post-layout simulations, including parasitic, demonstrate for conventional CCDD circuits that TFET technology has a larger dynamic range (DR) (>60%) and better 1 V-sensitivity than the 32 nm planar technology has. Note that, in this case, the figure of merit defined by the Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) remains somewhat similar. On the other hand, topology proposing better VCE at the cost of low PCE shows lower performance than expected in 32 nm than in reported data for larger technology nodes (e.g., 180 nm). The TFET-based circuit shows a PCE of 70%, VCE of 82% with an 8 dB DR (>60%), and the best 1 V-sensitivity in this work. Because of the low-bias condition and the good reverse current blocking (unidirectional channel), the TFET offers new perspectives for RF-DC rectifier/multiplier topology, which are usually limited with planar technology.

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“…To extend the benefits of the Moore's law, highly complex and expensive innovative fabrication processes as well as new logical schemes are required . In this regard, several different alternative logic gates have been investigated, such as nanotube gates, 2D materials logic gates, quantum logic gates, and biocircuits . For instance, quantum logic gates are scalable using existing silicon technologies, but they demand very low working temperatures .…”

Section: Introductionmentioning

confidence: 99%

Bottom‐Gate Approach for All Basic Logic Gates Implementation by a Single‐Type IGZO‐Based MOS Transistor with Reduced Footprint

Cunha

Guo

et al. 2020

Advanced Science

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Logic functions are the key backbone in electronic circuits for computing applications. Complementary metal‐oxide‐semiconductor (CMOS) logic gates, with both n‐type and p‐type channel transistors, have been to date the dominant building blocks of logic circuitry as they carry obvious advantages over other technologies. Important physical limits are however starting to arise, as the transistor‐processing technology has begun to meet scaling‐down difficulties. To address this issue, there is the crucial need for a next‐generation electronics era based on new concepts and designs. In this respect, a single‐type channel multigate MOS transistor (SMG‐MOS) is introduced holding the two important aspects of processing adaptability and low static dissipation of CMOS. Furthermore, the SMG‐MOS approach strongly reduces the footprint down to 40% or even less area needed for current CMOS logic function in the same processing technology node. Logic NAND, NOT, AND, NOR, and OR gates, which typically require a large number of CMOS transistors, can be realized by a single SMG‐MOS transistor. Two functional examples of SMG‐MOS are reported here with their analysis based both on simulations and experiments. The results strongly suggest that SMG‐MOS can represent a facile approach to scale down complex integrated circuits, enabling design flexibility and production rates ramp‐up.

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2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs

Cited by 32 publications

References 14 publications

Model for Predicting the Threshold Voltage of Tunnel Field-Effect Transistors Using Linear Regression

Model for Predicting the Threshold Voltage of Tunnel Field-Effect Transistors Using Linear Regression

From 32 nm to TFET Technology: New Perspectives for Ultra-Scaled RF-DC Multiplier Circuits

Bottom‐Gate Approach for All Basic Logic Gates Implementation by a Single‐Type IGZO‐Based MOS Transistor with Reduced Footprint

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