20.10 A 68.1-to-96.4GHz variable-gain low-noise amplifier in 28nm CMOS

Vigilante, Marco; Reynaert, Patrick

doi:10.1109/isscc.2016.7418056

Cited by 54 publications

(19 citation statements)

References 6 publications

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“…9 with different values of k. It can be seen that for lower k, the two resonances come closer to each other. This feature is useful for wideband amplifier designs as in [15] and [3]. However, when the k is increased separation between two resonances starts to increase which is a suitable criteria for narrowband amplifier designs.…”

Section: Applying Transformers In Mmwave Ic Designsmentioning

confidence: 99%

Design of a 40 GHz low noise amplifier using multigate technique for cascode devices

Shaheen

Rahkonen

Pärssinen

2020

Analog Integr Circ Sig Process

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Increased parasitic components in silicon-based nanometer (nm) scale active devices have various performance trade-offs between optimizing the key parameters, for example, maximum frequency of oscillation ($$f_{max}$$ f max , gate resistance and capacitance, etc. A common-source cascode device is commonly used in amplifier designs at RF/millimeter-wave (mmWave) frequencies. In addition to intrinsic parasitic components, extrinsic components due to wiring and layout effects, are also critical for performance and accurate modelling of the devices. In this work, a comparison of two different layout techniques for cascode devices is presented to optimize the extrinsic parasitic elements, such as gate resistance. A multi-gate or multi-port layout technique is proposed for optimizing the gate resistance ($$r_g$$ r g ). Extracted values from measurement results show reduction of 10% in $$r_{g}$$ r g of multi-gate layout technique compared to a conventional gate-above-device layout for cascode devices. However, conventional layout exhibits smaller gate-to-source and gate-to-drain capacitances which leads to better performance in terms of speed, i.e. $$f_{max}$$ f max . An LNA is designed at 40 GHz frequency using proposed multi-gate cascode device. LNA achieves a measured peak gain of 10.2 dB and noise figure of 4.2 dB at 40 GHz. All the structures are designed and fabricated using 45 nm CMOS silicon on insulator (SOI) technology.

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Section: Applying Transformers In Mmwave Ic Designsmentioning

confidence: 99%

Design of a 40 GHz low noise amplifier using multigate technique for cascode devices

Shaheen

Rahkonen

Pärssinen

2020

Analog Integr Circ Sig Process

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“…The LNA is one of the key components in a communication system because it mainly determines the noise performance of the receiver chain. The common source stage is widely used in LNA designs for its high gain and low noise [1,2,3]. To improve the gain and counteract the Miller effect, cross-coupled capacitors are always added in the CS stage [1,4].…”

Section: Introductionmentioning

confidence: 99%

“…The common source stage is widely used in LNA designs for its high gain and low noise [1,2,3]. To improve the gain and counteract the Miller effect, cross-coupled capacitors are always added in the CS stage [1,4]. Another way of using capacitors which are called gm-boosted technique is introduced in [5].…”

Section: Introductionmentioning

confidence: 99%

A 24 GHz enhanced neutralized cascode LNA with 4.7 dB NF and 19.8 dB gain

Jiang

Liu

et al. 2018

IEICE Electron. Express

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This paper presents a two-stage low noise amplifier (LNA) for 24 GHz automotive radar applications. Compared with traditional common source (CS) stage, the neutralized topology is used to improve the gain and reverse isolation in the first stage. In the second stage, an enhanced neutralized technique is adopted to improve the gain further. The LNA is fabricated by using standard 180-nm CMOS technology and occupies a chip area of 1.0 × 0.8 mm 2. The design realizes a gain of 19.8 dB, a noise figure (NF) of 4.7 dB and an input 1 dB compression point (IP 1dB) of −12 dBm.

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“…1 shows the schematic of the proposed two-stage PA. Each transconductor stage is realized with neutralized CS amplifiers. A 2-way transformer-based series power combiner and divider derived from a broadband 4 th order filter are employed to enhance the gain-BW product, without adding extra lossy components [5]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…2 shows the proposed circuit transformation adopted to realize the required 1/n impedance scaling at the output. Given the low RC product of load, imposed by the 50Ω termination, k o should be designed as high as possible to realize impedance transformation over the desired bandwidth (see ( 1 ) while k o is swept realizing a larger band-pass bandwidth [5]. A symmetrically driven 2-way series power combiner can be easily derived from the 2-port 4 th order filter as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A 29-to-57GHz AM-PM compensated class-AB power amplifier for 5G phased arrays in 0.9V 28nm bulk CMOS

Vigilante

Reynaert

2017

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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Abstract-This paper presents a 29-to-57GHz (65% BW) AM-PM compensated class-AB power amplifier tailored for 5G phased arrays. Designed in 0.9V 28nm CMOS without RF thick top metal, the PA achieves a Psat=15.1dBm±1.6dB and │AM-PM│<1° from 29-to-57GHz, with a peak PAE of 24.2%. Techniques are studied to realize the required load impedance and distortion cancellation over the wide band of operation, while allowing 2-way power combining to further increase the delivered POUT. The very low AM-PM distortion of the realized PA enables up to 10.1, 8.9, 5.9dBm average POUT while amplifying a 1.5, 3, 6Gb/s 64-QAM respectively at 34GHz with EVM/ACPR better than -25dBc/-30dBc, without any digital pre-distortion.Index Terms-5G mobile communication, power amplifiers, AM-PM, broadband, wideband, coupled resonators, gain-bandwidth product, GBW, mm-Wave, CMOS. I. INTRODUCTIONThe frequency spectrum above 24GHz will be a key enabler for future Gb/s fifth generation (5G) wireless communication systems [1,2]. To maximize the data rate, high order modulation schemes (e.g. 64-QAM) with large RF bandwidth (>100MHz) will be adopted. At the transmitter side, this implies several design challenges. 1) A wideband PA is needed to cover several channels, amplify wideband signals and ensure robust performance against PVT variations. 2) Modulated signals with high spectral efficiency show large peak-to-average-powerratio, challenging the linearity vs. efficiency trade-off for a given average P OUT . 3) Digital pre-distortion is not easily applicable when several PAs are integrated in an array [1]. Therefore, techniques to compensate AM-PM distortion over a large bandwidth are desirable to improve both inband and out-of-band linearity (i.e. EVM and ACPR).Recently, the work in [1] has shown the feasibility of 28GHz CMOS PAs with outstanding efficiency. However, the BW, average P OUT and ACPR under modulated signal considerably limit the achievable link distance and coexistence with adjacent channels. 2

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20.10 A 68.1-to-96.4GHz variable-gain low-noise amplifier in 28nm CMOS

Cited by 54 publications

References 6 publications

Design of a 40 GHz low noise amplifier using multigate technique for cascode devices

Design of a 40 GHz low noise amplifier using multigate technique for cascode devices

A 24 GHz enhanced neutralized cascode LNA with 4.7 dB NF and 19.8 dB gain

A 29-to-57GHz AM-PM compensated class-AB power amplifier for 5G phased arrays in 0.9V 28nm bulk CMOS

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