Design of a 40 GHz low noise amplifier using multigate technique for cascode devices

Abstract

Increased parasitic components in silicon-based nanometer (nm) scale active devices have various performance trade-offs between optimizing the key parameters, for example, maximum frequency of oscillation ($$f_{max}$$ f max , gate resistance and capacitance, etc. A common-source cascode device is commonly used in amplifier designs at RF/millimeter-wave (mmWave) frequencies. In addition to intrinsic parasitic components, extrinsic components due to wiring and layout effects, are also critical for performance and accurate modelling of the devices. In this work, a comparison of two different layout techniques for cascode devices is presented to optimize the extrinsic parasitic elements, such as gate resistance. A multi-gate or multi-port layout technique is proposed for optimizing the gate resistance ($$r_g$$ r g ). Extracted values from measurement results show reduction of 10% in $$r_{g}$$ r g of multi-gate layout technique compared to a conventional gate-above-device layout for cascode devices. However, conventional layout exhibits smaller gate-to-source and gate-to-drain capacitances which leads to better performance in terms of speed, i.e. $$f_{max}$$ f max . An LNA is designed at 40 GHz frequency using proposed multi-gate cascode device. LNA achieves a measured peak gain of 10.2 dB and noise figure of 4.2 dB at 40 GHz. All the structures are designed and fabricated using 45 nm CMOS silicon on insulator (SOI) technology.

Blocker tolerant cascode LNA for Wifi & IoT applications

“…Gain is discovered to be smaller because of the work is intended for 60 GHz. Rana Azhar Shaheen et al 27 developed a multi‐port layout approach to optimize the gate resistance while conventional layout techniques minimized the wiring capacitance. Further, the technique was compared against cascode LNA's and the device was fabricated utilizing the 45 nm CMOS silicon‐on‐insulator (SOI) technology.…”