20–80nm Channel length InGaAs gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63mV/dec

Abstract

In this paper, 20nm -80nm channel length (L ch ) InGaAs gateall-around (GAA) nanowire MOSFETs with record high onstate and off-state performance have been demonstrated by equivalent oxide thickness (EOT) and nanowire width (W NW ) scaling down to 1.2nm and 20nm, respectively. SS and DIBL as low as 63mV/dec and 7mV/V have been demonstrated, indicating excellent interface quality and scalability. Highest I ON = 0.63mA/μm and g m = 1.74mS/μm have also been achieved at V DD =0.5V, showing great promise of InGaAs GAA technology for 10nm and beyond high-speed lowpower logic applications.

Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates

“…Based on the data presented in this paper we draw some general conclusions regarding III-V NWs and their implementation; although high intrinsic performance, that is high transconductance and drive currents, has been demonstrated in various forms of III-V nanowires [4] [14][15] [16], it is clear that the implementation of RFcompatible devices still is a challenge. Analysis of planar III-V MOSFETs [23] show that the control of the access resistance is one of the key parameters to increase the transconductance and to obtain attractive RF-properties.…”

“…Quantifying g m,peak -widths, the values for s-FETs and a-FETs do not differ, suggesting there is not a significant spread in V T within arrays that would cause a degraded maximum g m . For reference, we have benchmarked our data with other high performance InAs and InGaAs NW FETs; a 13 nm planar XOI FET, L G = 230 nm [14], a 25 nm diameter InAs/InP radial nanowire FET (Ω-gate, I DS,norm = I DS /(n·0.75π·D NW )), L G = 170 nm [15], a 15 nm in diameter lateral NW, L G = 100 [4], and a top down rectangular GGA FET (20x30 nm), L G = 20 nm [16].…”

Carbon-based nanomaterials

“…To achieve MOSFET-type or TFET characteristics requires doped source/drain regions, which are still somewhat difficult to achieve and control with uniformity in carbon-based systems. .16 Summary of the predicted TFET performance for CNTs and GNRs along with experimentally reported performance of Schottky barrier FETs consisting of 1.3 nm CNT and $2 nm wide GNR (Dey et al, 2013;Gu et al, 2012;Franklin et al, 2012a;Wang et al, 2008).…”

“…A comparison of the experimentally demonstrated performance of Schottky barrier CNTFETs with III-V MOSFET and T-FETs in Figure 8.9 reveals that today CNTFETs exhibit better on-state performance as compared to the rivaling III-V technologies (Zhou et al, 2012;Dey et al, 2013;Moselund et al, 2012;Hu, 2008;Wang et al, 2010;Ganapathi and Salahuddin, 2011;Gnani et al, 2011;Tomioka et al, 2012;Gu et al, 2012), however, the poor on-off ratio exhibited by the SB-CNTFETs reveals the need for short-channel carbon-based FETs with minimum off-state leakage. A number of obstacles need to be overcome before introducing CNTs into the mainstream manufacturing technology.…”

“…However, the ON-OFF ratio falls short of requirements for various ITRS technologies (http://www.itrs.net/Links/2012ITRS/Home2012.htm). The main reason for the poor off-state current is the leakage current through the Schottky barrier (Franklin et al, 2012a,b) and III-V devices (Gu et al, 2012;Dey et al, 2013) (Zhou et al, 2012;Dey et al, 2013;Moselund et al, 2012;Hu, 2008;Wang et al, 2010;Ganapathi and Salahuddin, 2011;Gnani et al, 2011;Tomioka et al, 2012). The ITRS targeted values for low operating power (LOP) and high performance (HP) technologies are highlighted (http://www.itrs.net/Links/2012ITRS/Home2012.htm).…”