“…Regarding the methods to construct III–V-on-Si architectures, a variety of studies have been reported. One of the most straightforward approaches would be the heteroepitaxial growth of GaAs-relevant materials on c-Si substrates; , however, despite the progress of elaborative buffer layer techniques to compensate for the difference in lattice constants and thermal expansion coefficients between GaAs and Si, the layer quality achieved with this type of approach remains a challenge. ,− Alternatively, bonding-based approaches have gained increasing attention, − and as previously mentioned, impressive results have already been obtained by mechanically stacked four-terminal tandems and surface-activation-bonded two-terminal tandems. , We have also developed a unique semiconductor bonding strategy, termed smart stack. − Using well-organized Pd nanoparticle (NP) arrays as bonding mediators, series-connected two-terminal tandem cells consisting of III–V and c-Si subcells have been successfully fabricated with the best efficiency of 30.8% . To make the smart stack technique more attractive, however, it would be preferable to find alternative materials for costly Pd, whose price has recently been rising due to the increasing demand of many other industrial applications…”