20 Years of reconfigurable field-effect transistors: From concepts to future applications

Mikolajick, Thomas; Galderisi, Giulio; Simon, Maik; Rai, Shubham; Kumar, Akash; Heinzig, André; Weber, Walter M.; Trommer, Jens

doi:10.1016/j.sse.2021.108036

Cited by 41 publications

(23 citation statements)

References 36 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…In parallel to this development, rising computing paradigms such as the “Internet of Things” and “artificial intelligence” are demanding the design of systems with even higher computational resources. In this regard, the functional diversification of transistors constitutes alternative approaches to enable novel system concepts enhancing state-of-the-art solutions. , To overcome the scaling limitation and therefore enhance novel device concepts, it is mandatory to implement new processes and device architectures to enable “more-than-Moore” paradigms extending the mature Si complementary metal–oxide semiconductor (CMOS) platform. A major prerequisite for a large number of emerging nanoelectronic, optoelectronic, and quantum devices are reliable and reproducible metal–semiconductor junctions.…”

Section: Introductionmentioning

confidence: 99%

Monolithic and Single-Crystalline Aluminum–Silicon Heterostructures

Wind

Böckle

Sistani

et al. 2022

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

Overcoming the difficulty in the precise definition of the metal phase of metal−Si heterostructures is among the key prerequisites to enable reproducible next-generation nanoelectronic, optoelectronic, and quantum devices. Here, we report on the formation of monolithic Al−Si heterostructures obtained from both bottom-up and top-down fabricated Si nanostructures and Al contacts. This is enabled by a thermally induced Al−Si exchange reaction, which forms abrupt and void-free metal−semiconductor interfaces in contrast to their bulk counterparts. The selective and controllable transformation of Si NWs into Al provides a nanodevice fabrication platform with high-quality monolithic and single-crystalline Al contacts, revealing resistivities as low as ρ = (6.31 ± 1.17) × 10 −8 Ω m and breakdown current densities of J max = (1 ± 0.13) × 10 12 Ω m −2 . Combining transmission electron microscopy and energy-dispersive X-ray spectroscopy confirmed the composition as well as the crystalline nature of the presented Al−Si−Al heterostructures, with no intermetallic phases formed during the exchange process in contrast to state-of-the-art metal silicides. The thereof formed single-element Al contacts explain the robustness and reproducibility of the junctions. Detailed and systematic electrical characterizations carried out on back-and top-gated heterostructure devices revealed symmetric effective Schottky barriers for electrons and holes. Most importantly, fulfilling compatibility with modern complementary metal−oxide semiconductor fabrication, the proposed thermally induced Al−Si exchange reaction may give rise to the development of nextgeneration reconfigurable electronics relying on reproducible nanojunctions.

show abstract

Section: Introductionmentioning

confidence: 99%

Monolithic and Single-Crystalline Aluminum–Silicon Heterostructures

Wind

Böckle

Sistani

et al. 2022

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

show abstract

“…Combined with the on‐ and off‐states, unipolar p‐ and n‐FET modes can be reversibly reconfigured with the dual‐gate FET. [ 53 ]…”

Section: Resultsmentioning

confidence: 99%

“…Combined with the on-and off-states, unipolar p-and n-FET modes can be reversibly reconfigured with the dual-gate FET. [53] The p-/n-type unipolarity is attributed to the carrier injection at the vdW contacts and the built-in field at the depletion region of the p-n homojunction. For simplification, the flatband voltage V fb is assumed to be 0 V in the following discussion.…”

Section: Resultsmentioning

confidence: 99%

Reconfigurable InSe Electronics with van der Waals Integration

Luo

Zhao

et al. 2022

Adv Elect Materials

View full text Add to dashboard Cite

As a 2D semiconductor, indium selenide (InSe) has shown great potentials in electronic and optoelectronic applications attributed to high carrier mobility and moderately large bandgap. However, switchable doping polarity of intrinsic InSe by electrical gating is not yet demonstrated, which is essential for applications in complementary electronics. In this work, the ambipolarity of InSe is realized and exploited through the van der Waals (vdW) integration with metal electrodes, which gets rid of the Fermi‐level pinning at the metal/semiconductor interfaces. On this basis, InSe field‐effect transistors (FETs) with controllable polarities are reconfigured with a dual‐gate structure, functioning as both unipolar FETs and p–n diodes. The p‐ and n‐type operations of the unipolar FETs are dynamically switched with on–off ratios of 106 and 109, respectively. Meanwhile, p–n diodes with a rectification ratio of 106 and high photodetection performance are also demonstrated. This work paves a promising way for InSe‐based reconfigurable complementary electronics and optoelectronics.

show abstract

“…Introduction: Given that tremendous transistors are required for contemporary machine learning processing and cutting-edge ICs, there is an urgent need to find solutions that address the issue of power consumption of semiconductor chips. To achieve this, several attempts have been made to find a new device such as a reconfigurable field-effect transistor (RFET) that can play either a n-or p-type metal-oxide semiconductor field-effect transistor(MOSFET) by a single transistor [1][2][3][4][5]. If an RFET can be realized and ideally incorporated in integrated circuits, the issue of chip density and power consumption can be substantially addressed because the number of transistors can be reduced, even not completely replaced.…”

mentioning

confidence: 99%

Analysis of temporal carrier build‐up in reconfigurable field‐effect transistor

Park

Lee

Kim

et al. 2021

Electronics Letters

View full text Add to dashboard Cite

Based on the analysis of the carrier density change of a symmetric gate reconfigurable field‐effect transistor that can operate p‐ or n‐type transistors in an integrated circuit (IC), its unique limiting factor, carrier build‐up time, is quantitatively derived for operating speed in addition to conventional resistance and capacitance (RC) and transit time effect. Originating from the characteristic of carrier confinement in a channel between two Schottky potential barriers, the carrier build‐up time for the operation could take up to ∼1000 times longer than the transit time across the channel.

show abstract

20 Years of reconfigurable field-effect transistors: From concepts to future applications

Cited by 41 publications

References 36 publications

Monolithic and Single-Crystalline Aluminum–Silicon Heterostructures

Monolithic and Single-Crystalline Aluminum–Silicon Heterostructures

Reconfigurable InSe Electronics with van der Waals Integration

Analysis of temporal carrier build‐up in reconfigurable field‐effect transistor

Contact Info

Product

Resources

About