20GHz Bandwidth Digitizer for Single Shot Analysis

Aabbaoui, Hassan El; Gorisse, B.; Rolland, N.; Benlarbi-Delaï, Aziz; Lampin, Jean‐François; Rolland, P.A.; Allouche, V.; Fel, N.; Riondet, Bernard; Leclerc, P.

doi:10.1109/iscas.2006.1693097

Cited by 2 publications

(2 citation statements)

References 4 publications

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“…Active devices have also been characterized by EAS: transistors, photodiodes [17] and logic circuits [18]. In this last case, the dc-bias voltage required for EAS is blocked by a series capacitor to avoid the breakdown of the circuit.…”

Section: Applicationsmentioning

confidence: 99%

Electro-absorption sampling at terahertz frequencies in III-V semiconductors

Lampin¹,

Desplanque²

2008

Comptes Rendus. Physique

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We review recent advances in the development of a new sampling technique for ultra high-speed electrical signals. It is based on the electro-absorption phenomena in semiconductors (Franz-Keldysh effect). We demonstrate that it is usable up to the terahertz range. The theory is exposed and we show two practical set-ups. The first uses the semiconductor substrate (internal sampling). The second uses a small semiconductor probe bonded on the circuit (external sampling). In this last case, the theoretical temporal resolution is about 200 fs. In practice, we measure a risetime of about 500 fs with 60 dB of dynamic range.

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Section: Applicationsmentioning

confidence: 99%

Electro-absorption sampling at terahertz frequencies in III-V semiconductors

Lampin¹,

Desplanque²

2008

Comptes Rendus. Physique

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“…On the other hand, tapped delay line techniques [16,17] (i.e. spatial sampling [18]) have been proven to be effective for transient signal digitization applications. The techniques exploit passive (off-chip) transmission lines (TL) for singleshot, short pulse ''storage'' followed by signal sampling with transmission-line based strobe-signal (i.e.…”

Section: Introductionmentioning

confidence: 99%

A high-speed sample-and-hold circuit based on CMOS transmission lines

Wang

Gao

et al. 2010

Analog Integr Circ Sig Process

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We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS TLs exhibit filter properties, which cause attenuation and deformation of signal pulses. Nevertheless, the dispersion effects on clock pulse propagation are minimal since clock lines are short, much shorter than the meandered input-signal line. Design considerations on clock pulse generator, sampling switches, and charge amplifiers are presented. Compared with other CMOS approaches, the proposed SHC generates clock pulses on chip and avoids clock jitter difficulties. The SHC is implemented in a 0.13 lm digital CMOS process with standard on-chip coplanar waveguides (CPW) as signal and clock pulse propagation TLs, silicon N-type field effect transistors (NFET) as sampling switches, and high-frequency charge amplifiers for charge amplification. Clock pulse signals of *50 ps width with *17 ps fall edge are generated on-chip. Simulation analysis with Cadence Spectre shows that a sampling rate of 20 Gigasample/s with a 25 dB spurious free dynamic range (SFDR) can be achieved. With shorter clock pulses, both sampling rate and SFDR can be improved in future design.

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20GHz Bandwidth Digitizer for Single Shot Analysis

Cited by 2 publications

References 4 publications

Electro-absorption sampling at terahertz frequencies in III-V semiconductors

Electro-absorption sampling at terahertz frequencies in III-V semiconductors

A high-speed sample-and-hold circuit based on CMOS transmission lines

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