This paper presents the design of a 60 GHz fully Monolithic Integrated Millimeter Wave Reflectometer (MIMWR). Active devices and passive planar structures are associated to realize a complete reflectometer on a single chip. The chip, that includes a six-port network, detectors and a Voltage Control Oscillator (VCO), is conceived by means of an InP-based technology from the OMMIC foundry. This system associated to a calibration technique that encompasses a linearization method of the detectors allows measurements of complex reflection coefficients.

Targeting bandwidth and 40 GS/s sampling rate for high dynamic range (60 dB) ultra fast signal analysis, we present the preliminary experimental results obtained on InP-InGaAs-InP double heterojunction bipolar transistor based MMIC (FT = 180 GHz). The critical circuits leading to wide band signal sampling operation are made of high bandwidth switched emitter follower (SEF) and high bandwidth buffer. They are realized and tested both in time and frequency domains. They exhibit performances in terms of isolation and bandwidth compatible with the targeted objectives.

The design of a single shot sampling circuit allowing II. SPATIAL SAMPLING PRINCIPLE 20GHz bandwidth random signal and the experimental resultsOriginal method allowing non simultaneous spatial of the main circuits are described. Assuming a temporal sampling for ultra fast electrical pulse has already been analysis depth of 5ns, this circuit, based on the principle of non described in [2], [3]. A schematic view of the sampling simultaneous spatial sampling and realized in InP HBT MMIC m is (FT=180GHz) and CPW propagation line, can reach a truly method is presented in Fig.1 in case of 8 sampling lines. sampling frequency of 40GS/s. Very good performances are expected using such a technology in terms of bandwidth, ignal edge propagation dynamic range and jitter. Moreover a specific test bench 3rd satp allowing very low jitter measurement is presented.

The aim of this paper is to demonstrate the good jitter performances of samplers based on a propagation line. Targeting high resolution and high bandwidth (10 effective bits at 8 GHz and 20 GHz bandwidth) two of these architectures have been adapted to large temporal sampling windows. As the trigger structures consist of inverters, the jitter of an elementary inverter is optimized and a delay cell is simulated and compared to measurements. Jitter of the two trigger structures is discussed. I. INTRODUCTIONRecent years have seen the incoming of a large panel of new high bandwidth sampling systems [1]-[6]. Many applications are concerned such as UWB communications, software radio and nuclear experiments. But most of the time the resolution of these systems is lower than 5 effective bits and big volume and energy are required, especially for optical solutions [1]- [3]. The main goal of our study is to improve the resolution of sampling systems, expecting 10 effective bits at 8 GHz with a 20 GHz bandwidth. Promising results were obtained with samplers based on a propagation line [7]-[9] but they have only been used for single shot applications. In order to use these architectures for large temporal sampling windows, this work deals with trigger structures.To reach very good performances, InP-InGaAs-InP Double Heterojunction Bipolar Transistors (DHBT) have been chosen. This technology provides very short rise and fall time (less than 10 ps on a 50 Ω matched load), low noise and high breakdown voltages. According to [12] it appears to be the most efficient technology for high performances samplers and results of a subsampling track-and-hold amplifier using InP SHBT confirm this figure, [13].Three main parameters influence sampler performances: noise, non-linearity and jitter. At high frequency the jitter effects are prevailing and this parameter in the trigger structure will be studied herein. This work first describes the two sampling architectures chosen to achieve good performances. As the trigger structure is composed of inverters, in a second part the jitter of inverters is discussed and compared to measured results. Finally the trigger structures of the two studied architectures are detailed and simulated. InP DHBT technology of the OMMIC foundry was used for these designs.

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