20GHz Operation of an Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit

Filippov, T.V.; Sahu, Anubhav; Kirichenko, A.F.; Vernik, Igor V.; Dorojevets, Mikhail; Ayala, Christopher L.; Mukhanov, Oleg A.

doi:10.1016/j.phpro.2012.06.130

Cited by 104 publications

(22 citation statements)

References 16 publications

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“…R APID Single Flux Quantum (RSFQ) technology [1] offers unmatched clock speed and low power dissipation [2]- [4]. Recently, its power dissipation was further reduced with an introduction of energy-efficient single flux quantum logics [5]- [8], making these circuits viable contenders for the implementation of next generation high performance computing (HPC) [9], cryogenic sensor image processors, and highend instrumentation.…”

Section: Introductionmentioning

confidence: 99%

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Vernik

Bolginov

Bakurskiy

et al. 2013

IEEE Trans. Appl. Supercond.

146

105

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We investigate a Magnetic Josephson Junction (MJJ) -a superconducting device with ferromagnetic barrier for a scalable high-density cryogenic memory compatible with energyefficient single flux quantum (SFQ) circuits. The superconductorinsulator-superconductor-ferromagnet-superconductor (SIS FS) MJJs are analyzed both experimentally and theoretically. We found that the properties of SIS FS junctions fall into two distinct classes based on the thickness of S layer. We fabricate Nb-Al/AlOx-Nb-PdFe-Nb SIS FS MJJs using a co-processing approach with a combination of HYPRES and ISSP fabrication processes. The resultant SIS FS structure with thin superconducting S -layer is substantially affected by the ferromagnetic layer as a whole. We fabricate these type of junctions to reach the device compatibility with conventional SIS junctions used for superconducting SFQ electronics to ensure a seamless integration of MJJ-based circuits and SIS JJ-based ultra-fast digital SFQ circuits. We report experimental results for MJJs, demonstrating their applicability for superconducting memory and digital circuits. These MJJs exhibit I c R n product only ∼30% lower than that of conventional SIS junctions co-produced in the same fabrication. Analytical calculations for these SIS FS structures are in a good agreement with the experiment. We discuss application of MJJ devices for memory and programmable logic circuits.Index Terms-Energy efficient, memory devices, proximity effect, RAM, single flux quantum, superconducting logic elements.

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Section: Introductionmentioning

confidence: 99%

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Vernik

Bolginov

Bakurskiy

et al. 2013

IEEE Trans. Appl. Supercond.

146

105

View full text Add to dashboard Cite

show abstract

“…L(S(i, m)) is the latency of the instruction which creates the m th source register of instruction i. Our experiments explore a range of non-ALU datadependent operation latencies [1,10] but in each individual experiment, for simplicity, we assume that all non-ALU operations have the same integral latency. As two examples, Fig.…”

Section: B Performance Evaluation: Instruction Per Cyclementioning

confidence: 99%

“…Various 8-bit SFQ microprocessors have been developed in the last two decades, including a bit-serial microprocessor with eight 1-bit serial ALU blocks (FLUX-1) [6], a bit-serial CORE1 processor [7], and a bit-serial SCRAM2 asynchronous microprocessor [8]. More specifically, the arithmetic logic unit (ALU), a critical part of a microprocessor, has gained significant research importance in RSFQ [9], [10], [11], [12]. Recently Tang et.…”

Section: Introductionmentioning

confidence: 99%

qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit

Kundu

Datta

Beerel

et al. 2019

2019 IEEE International Superconductive Electronics Conference (ISEC)

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Single flux quantum (SFQ) circuits are an attractive beyond-CMOS technology because they promise two orders of magnitude lower power at clock frequencies exceeding 25 GHz. However, every SFQ gate is clocked creating very deep gatelevel pipelines that are difficult to keep full, particularly for sequences that include data-dependent operations. This paper proposes to increase the throughput of SFQ pipelines by redesigning the datapath to accept and operate on least-significant bits (LSBs) clock cycles earlier than more significant bits. This skewed datapath approach reduces the latency of the LSB side which can be feedback earlier for use in subsequent datadependent operations increasing their throughput. In particular, we propose to group the bits into 4-bit blocks that are operated on concurrently and create block-skewed datapath units for 32bit operation. This skewed approach allows a subsequent datadependent operation to start evaluating as soon as the first 4bit block completes. Using this general approach, we develop a block-skewed MIPS-compatible 32-bit ALU. Our gate-level Verilog design improves the throughput of 32-bit data dependent operations by 2x and 1.5x compared to previously proposed 4bit bit-slice and 32-bit Ladner-Fischer ALUs respectively. We have quantified the benefit of this design on instructions per cycle (IPC) for various RISC-V benchmarks assuming a range of non-ALU operation latencies from one to ten cycles. Averaging across benchmarks, our experimental results show that compared to the 32-bit Ladner-Fischer our proposed architecture provides a range of IPC improvements between 1.37x assuming one-cycle non-ALU latency to 1.2x assuming ten-cycle non-ALU latency. Moreover, our average IPC improvements compared to a 32-bit ALU based on the 4-bit bit-slice range from 2.93x to 4x.Index Terms-Energy efficient computation, RSFQ, arithmetic logic unit (ALU), block-skewed architecture.

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“…Recently, we have demonstrated an 8-bit arithmetic-logic unit (ALU) operating at 20 GHz [7], [8]. In order to build a processor datapath, it has to be integrated with a compatible register file.…”

Section: Introductionmentioning

confidence: 99%

Demonstration of an 8×8-bit RSFQ multi-port register file

Kirichenko

Sahu

Filippov

et al. 2013

2013 IEEE 14th International Superconductive Electronics Conference (ISEC)

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As a part of the 8-bit RSFQ processor datapath development, we have designed, fabricated, and experimentally demonstrated an 8x8-bit RSFQ multi-port register file. The register file provides input data operands and stores Arithmetic Logic Unit (ALU) results. It can perform two simultaneous nondestructive "read" operations and one "write" operation and is capable of storing eight 8-bit words. The distinct feature of the design is an extensive use of passive transmission lines (PTLs) for very complex interconnects inside the register file. The register file is designed for integration with recently demonstrated 20-GHz 8-bit RSFQ ALU. It is fabricated with the standard HYPRES's 1.0-um 4.5-kA/cm 2 process. The circuit is placed on a 1 cm x 1 cm chip and consists of ~4,000 Josephson junctions.

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20GHz Operation of an Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit

Cited by 104 publications

References 16 publications

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit

Demonstration of an 8×8-bit RSFQ multi-port register file

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20GHz Operation of an Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit

Cited by 104 publications

References 16 publications

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit

Demonstration of an 8&#x00D7;8-bit RSFQ multi-port register file

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Demonstration of an 8×8-bit RSFQ multi-port register file