21.3: A Novel 5‐Mask Etch‐Stopper Pixel Structure with A Short Channel Oxide Semiconductor TFT

Abstract

In order to solve the main issues of etch-stopper (ES) pixel structure (mask steps, parasitic capacitance Cgs, TFT channel length) in a-IGZO pixel structure of AMLED, new 5-mask ES a-IGZO pixel structure was investigated. TFT channel length of 5 μm could be achieved by self-aligned damage preventing layer. We could achieve good characteristics and reliability of short-channellength (under 5 μm) ES TFTs. And also Cgs could be reduced more than 30%.

Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

“…Moreover, this increased number of thin film layers would increase the inter-layer overlap area and result in the increased parasitic capacitance and decreased opening ratio [ 16 – 18 ]. Although five-mask ES process that produces TFT backplane using half-tone and lift-off technology has been reported recently, this process is not accessible for the production of a-IGZO-based TFT backplane, as their active layer surface is still exposed to process chemicals such as stripper and photoresist in the last step, which may cause considerable contamination to a-IGZO, thus reducing the device quality and the production yield [ 19 – 21 ]. Therefore, the industrial production method for a-IGZO-based TFT backplane with highly uniformity and stability remains challenging.…”