22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

Miyahara, Masaya; Mano, Ibuki; Nakayama, Masaaki; Okada, Kei; Matsuzawa, Akira

doi:10.1109/isscc.2014.6757482

Cited by 47 publications

(10 citation statements)

References 5 publications

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“…shows the range of the power consumed by different devices included in a mmWave front-end. Data were taken from a number of recent papers proposing protoype devices for PAs[84]-[87], LNAs[88]-[91], phase shifters[92]-[98], VCOs[99]-[101] and ADCs[102]-[108] at mmWave frequencies. L t (L r ) is the number of RF chains at the TX(RX).…”

mentioning

confidence: 99%

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

Heath

González–Prelcic

Rangan

et al. 2016

IEEE J. Sel. Top. Signal Process.

2,507

1,760

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mentioning

confidence: 99%

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

Heath

González–Prelcic

Rangan

et al. 2016

IEEE J. Sel. Top. Signal Process.

2,507

1,760

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“…In this way, the input voltage of each comparator is now determined by the devices of a few pre-amplifiers instead of just one, and this allows reducing the area of individual components. Examples of recent ADCs resorting to these techniques are [62,[116][117][118]. Reference [119] provided an exhaustive study on the application of this technique to flash ADCs.…”

Section: Adcs Without Residue Amplificationmentioning

confidence: 99%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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“…Since this architecture replaces analog functional blocks with digital circuits, we anticipate that it will reduce the power consumption and scale favorably in advanced technology nodes. This approach can be viewed as a generalization of recent work exploiting timing difference between comparators in a flash design [2] [3].…”

Section: Introductionmentioning

confidence: 99%