2020
DOI: 10.1049/el.2019.4105
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22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time‐to‐digital converter in CMOS 65 nm for single photon avalanche diode array

Abstract: A Vernier ring-oscillator-based time-to-digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of 0.00151 mm 2. Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to 22 mW at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission… Show more

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Cited by 12 publications
(12 citation statements)
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“…Recent developments in PET instrumentation include very fast SiPM [10] that can be read out by sub-10-ps time-todigital converters (TDCs) [11]. These advances have a high technological readiness level, meaning that they will soon be deployable in an industrial scale.…”
Section: B Pet Detectorsmentioning
confidence: 99%
“…Recent developments in PET instrumentation include very fast SiPM [10] that can be read out by sub-10-ps time-todigital converters (TDCs) [11]. These advances have a high technological readiness level, meaning that they will soon be deployable in an industrial scale.…”
Section: B Pet Detectorsmentioning
confidence: 99%
“…It has an excellent energy and position resolution and PID capabilities (5D calorimeter). The scintillation and the Čerenkov lights are read out by on-tile SiPMs [139] or SPAD [140][141][142][143][144][145]. The SPAD timing resolution (15 ps), based on Single-Photon Avalanche Diode arrays, can be exploited for ToF measurements and as input to the Level-0 trigger.…”
Section: Accelerated Particles: Protonsmentioning
confidence: 99%
“…The selection of the CMOS process should take into account the SPAD characteristics, such as the bias excess voltage the front-end electronics will need to quench, the size of the SPAD wafers to match with the CMOS wafers for 3D integration, the SPAD size constraining the size of front-end electronics for each SPAD, the complexity of the desired digital signal processing embedded in the ASIC, the cost and the availability of MPW runs. For instance, in the specific case of ToF-PET imaging, a TDC with sub-10 ps FWHM is desirable and points toward more advanced CMOS processes [ 48 , 129 , 132 , 133 ]. In the case of noble liquid detectors, very large area must be covered with maximum fill-factor and minimal power consumption to prevent boiling and convection of the noble liquid [ 12 , 66 ].…”
Section: Perspective Of 3d Pdc For Radiation Instrumentationmentioning
confidence: 99%
“…In theory, one TDC per SPAD-QC seems the best choice since it allows for correction of the timing skew of each pixel of a SPAD-QC-TDC. However, it comes with many challenges such as limited area (< ) and power consumption per TDC (< 100 W) [ 133 , 145 ].…”
Section: Perspective Of 3d Pdc For Radiation Instrumentationmentioning
confidence: 99%
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