22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

Narasimha, S.; Chang, P.; Ortolland, C.; Fried, D.; Engbrecht, E. R.; Nummy, Karen; Parries, P.; Ando, Takashi; Aquilino, Michael; Arnold, N.; Bolam, R.; Cai, Jin; Chudzik, M.; Cipriany, B.; Costrini, G.; Dai, Min; Dechene, J.; DeWan, C.; Engel, Brad N.; Gribelyuk, M.; Guo, Dechao; Han, Geng; Habib, Nazmul; Holt, J.; Ioannou, D.P.; Jagannathan, B.; Jaeger, D.; Johnson, J. B.; Kong, Weiran; Koshy, J.; Krishnan, R.; Kumar, Arvind; Kumar, M.; Lee, J.; Li, X.; Chen, Lin; Linder, B.; Lucarini, Stephen; Lustig, N.; McLaughlin, P.; Onishi, K.; Ontalus, V.; Robison, Robert R.; Sheraw, C.; Stoker, M. W.; Thomas, A.; Wang, G.; Wise, Rich; Zhuang, Larry; Freeman, G.; Gill, Jason M.R.; Maciejewski, E.; Malik, R.; Norum, J.; Agnello, P.

doi:10.1109/iedm.2012.6478971

Cited by 71 publications

(35 citation statements)

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“…This is consistent with the modeled high capacitance in 3D structures [22], and with the long L (27-33 nm) and high variability that have been the result of doped fully-depleted devices. The deviations in the existing 22 nm FinFET implementation from the ideal FinFET (Table 4) is depicted in Table 5.…”

Section: -Requirements For Scalabilitysupporting

confidence: 86%

“…In addition to the excess capacitance caused by longer L and/or the heavily doped bottom of the FinFET, there is also large parasitic capacitance between gate-source and gate-drain [22]. In a 14 nm technology, at reduce fin pitch and reduced CPP, because of the increased parasitic capacitance and possible increase in variability, at the product level, it will be probably challenging to obtain performance gain (i.e.…”

Section: Impact Implicationmentioning

confidence: 98%

“…There is another implementation of a high performance 22 nm node technology, this based on 2D planar device [22]. This technology has faster devices (i.e.…”

Section: -Performance Implication Of Existing 22 Nm Finfet Implemementioning

confidence: 99%

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From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Shahidi

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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The microelectronics industry is in the process of transitioning from 2D-planar devices to 3D-non-planar (FinFET). In this paper, a metric is developed to assess the impact of scaling and device performance on chip (circuit) power as it is migrated node-to-node. The impact of node migration is assessed at product level as it is moved from 32 nm (2D-planar) to 22 nm (3D-non-planar device). Some of the limitations of the existing 22 nm 3D-device is reviewed that may explain some of the short comings in the product performance. Going forward it is critical that in two areas the FinFET needs to be improved: Multi-V T implementation and move away from the tapered fin shape.

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Section: -Requirements For Scalabilitysupporting

confidence: 86%

Section: Impact Implicationmentioning

confidence: 98%

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From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Shahidi

2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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“…(In order to estimate Eox from published data plotted vs. Vov. the T inv value for the IBM 32 nm was taken from [38]). …”

Section: Process-and Architecture-independent Resultsmentioning

confidence: 99%

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Franco

Kaczer

Mitard

et al. 2013

IEEE Trans. Device Mater. Relib.

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Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a SiO 2 /HfO 2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups.

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“…Commodity DDR3 (2007) [14]; DDR4 (2012) [18] Low-Power LPDDR3 (2012) [17]; LPDDR4 (2014) [20] Graphics GDDR5 (2009) [15] Performance eDRAM [28], [32]; RLDRAM3 (2011) [29] 3D-Stacked WIO (2011) [16]; WIO2 (2014) [21]; MCDRAM (2015) [13]; HBM (2013) [19]; HMC1.0 (2013) [10]; HMC1.1 (2014) [11] Academic SBA/SSA (2010) [38]; Staged Reads (2012) [8]; RAIDR (2012) [27]; SALP (2012) [24]; TL-DRAM (2013) [26]; RowClone (2013) [37]; Half-DRAM (2014) [39]; Row-Buffer Decoupling (2014) [33]; SARP (2014) [6]; AL-DRAM (2015) [25] At the forefront of such innovations should be DRAM simulators, the software tool with which to evaluate the strengths and weaknesses of each new proposal. However, DRAM simulators have been lagging behind the rapid-fire changes to DRAM.…”

Section: Segment Dram Standards and Architecturesmentioning

confidence: 99%

Ramulator: A Fast and Extensible DRAM Simulator

Kim

Yang

Mutlu

2016

IEEE Comput. Arch. Lett.

523

228

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Abstract-Recently, both industry and academia have proposed many different roadmaps for the future of DRAM. Consequently, there is a growing need for an extensible DRAM simulator, which can be easily modified to judge the merits of today's DRAM standards as well as those of tomorrow. In this paper, we present Ramulator, a fast and cycle-accurate DRAM simulator that is built from the ground up for extensibility. Unlike existing simulators, Ramulator is based on a generalized template for modeling a DRAM system, which is only later infused with the specific details of a DRAM standard. Thanks to such a decoupled and modular design, Ramulator is able to provide out-of-the-box support for a wide array of DRAM standards: DDR3/4, LPDDR3/4, GDDR5, WIO1/2, HBM, as well as some academic proposals (SALP, AL-DRAM, TL-DRAM, RowClone, and SARP). Importantly, Ramulator does not sacrifice simulation speed to gain extensibility: according to our evaluations, Ramulator is 2.5× faster than the next fastest simulator. Ramulator is released under the permissive BSD license.

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22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL

Cited by 71 publications

References 0 publications

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

NBTI Reliability of SiGe and Ge Channel pMOSFETs With $ \hbox{SiO}_{2}/\hbox{HfO}_{2}$ Dielectric Stack

Ramulator: A Fast and Extensible DRAM Simulator

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