23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications

Balakrishnan, Mani; Brox, M.; Chetreanu, Cristian; Dietrich, Stefan; Funfrock, Fabien; Gonzalez, Marcos Alvarez; Hein, Thomas; Huber, Eugen; Lauber, Daniel; Ivanov, Milena; Kuzmenka, Maksim; Mohr, Chris; Munoz, Francisco Emiliano; Garrido, Juan Ocon; Padaraju, Swetha; Piatkowski, Sven; Pottgiesser, Jan; Pfefferl, Peter; Plan, Manfred; Polney, Jens; Rau, Stefan; Richter, Michael; Schneider, Ronny; Seitter, Ralf Oliver; Spirkl, W.; Walter, Marc D.; Weller, Jörg; Vitale, Filippo

doi:10.1109/isscc.2017.7870424

Cited by 11 publications

(2 citation statements)

References 3 publications

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“…While 1 bit-write enable bit densities (47Gb/cm² at F=15nm) almost competitive with planar Flash NAND densities (76Gb/cm² for F=16nm [30], 56Gb/cm² for F=19nm [34] and 28Gb/cm² for F=32nm [35]), 16 and 32 bit-write per array strongly reduce the bit density (less than 5Gb/cm² for 16 bitwrite at F=15nm) lower than DRAM density (9.4Gb/cm² for F=20nm [36] and 3.8Gb/cm² for F=37nm [37]). This result highlights the need for write a small number of bits per array in order to maximize the density.…”

Section: Discussionmentioning

confidence: 96%

Architecture, design and technology guidelines for crosspoint memories

Levisse

Royer

Giraud

et al. 2017

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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While standalone Flash memories (NAND) are facing their physical limitations, the emergence of resistive switching memories (RRAM) is seen as a solution for high density, low cost and low energy NAND replacement candidate. However, it has been shown that deeply scaled, high density RRAM architectures, such as crosspoint, suffer of voltage drop effects (IR drop) in metal lines, periphery overhead and metal line charging time due to injected current during programming operations and sneaking currents through unselected bitcells. In this work, we first propose several innovative models for IRdrop, periphery overhead and array-line charging time accounting for in-array multiple bit-write operation. Then, we introduce a new methodology for crosspoint memory design to determine IRdrop, periphery overhead and timing associated with the optimal characteristics of 1 selector-1 resistance (1S1R) device. We apply the proposed methodology to various half metal pitch memory technology nodes (from 50nm to 15nm) and to several written word sizes (from 1 to 32 bits). We show that for 1 bit programmed per array, the RRAM programming current has to be lower than 30µA and the selector leakage current lower than 10nA and that limitations increase as soon as multiple bits are written simultaneously in the same array. This, suggests massively parallel multi-bank write of a small number of bits per array, as the best solution for the RRAM memories to be competitive with NAND memories

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Section: Discussionmentioning

confidence: 96%

Architecture, design and technology guidelines for crosspoint memories

Levisse

Royer

Giraud

et al. 2017

2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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“…This way, more than 80% of area efficiency can be achieved (the considered densities are the following 76Gb/cm² for F=16nm [24], 56Gb/cm² for F=19nm [25] and 28Gb/cm² for F=32nm [26] and for 3D VNAND [1] more than 200Gb/cm 2 while considering a relaxed pitch higher than 40nm). On the other hand, due to charge sharing effect between the accessed cells and the BLs, DRAM density is limited (the considered bit densities are 9.4Gb/cm² for F=20nm [27] and 3.8Gb/cm² for F=37nm [28]). When compared to Flash NAND memories, due to huge area overhead, crosspoint memories exhibit lower bit density although the bitcell area is the same (4F²).…”

Section: Crosspoint Positionningmentioning

confidence: 99%

RRAM Crossbar Arrays for Storage Class Memory Applications: Throughput and Density Considerations

Levisse

Giraud

Noël

et al. 2018

2018 Conference on Design of Circuits and Integrated Systems (DCIS)

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As more and more high density memories are required to satisfy the Internet of Things ecosystem, academics and industrials are looking for an intermediate solution to fill the gap between DRAM and Flash NAND in the memory hierarchy. The emergence of Resistive Switching Technologies (RRAM) proposes a potential solution to this demand for fast, low cost, high density and non-volatile memory. However, nowadays transistorless RRAM-based architectures, such as Crosspoint, suffers of several issues such as sneakpath, IRdrop and periphery overhead. In this work, we propose to explore the positioning of RRAM crosspoint memories regarding DRAM and NAND in terms of density and write throughput. We present several design guidelines then show that for the optimal RRAM crosspoint architecture (2-layers with common bitline), massively multiple bank write is the solution to optimize density and write throughput to around 20-100Gbit/cm2 and 200-500MB/s respectively for 32 to 64 parallel access.

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