24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

Fujiwara, Haruhiko; Lin, Chih‐Yu; Pan, Hsien-Yu; Lin, Chun-Hsiung; Huang, Peter; Lin, Ku-Feng; Liaw, J.J.; Chen, Yen-Huei; Liao, Haijun; Chang, Jonathan

doi:10.1109/isscc.2019.8662415

Cited by 11 publications

(3 citation statements)

References 3 publications

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“…If read/write operations are performed simultaneously to generate conflicts, it will lead to read and write operations for the same memory The problem of read/write conflict has been extensively studied in the field of integrated circuits. For instance by Suzuki et al [23] introduced a novel cell bias technique to mitigate the effect of read/write interference; [24] enhanced the WordLine-Resistance/Capacitor and refined the logic to reduce the read/write conflict issue. Based on the theoretical analysis, this paper proposes an optimized circuit structure design to address the challenge of read and write conflicts.…”

Section: Read/write Conflict and Timing Error Mechanism Analysismentioning

confidence: 99%

A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit

Zhao,

Zhang,

Wen

et al. 2023

IET Circuits, Devices & Systems

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Register file (Regfile), as the bottleneck circuit for processor data interaction, directly determines the computing performance of the system. To address the read/write conflict and timing error problems of register heap, this paper proposes a 5R4W high-timing reliability Regfile circuit design scheme. First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. Experimental results show that the Regfile circuit has an area of 0.13 mm2 and consumes 5.541 mW. The circuit operates at a maximum frequency of 3.8 GHz at −40 to −125°C and 0.75 V, and is capable of detecting write errors caused by a clock jitter exceeding 30 ps or a frequency above 5 GHz.

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Section: Read/write Conflict and Timing Error Mechanism Analysismentioning

confidence: 99%

A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit

Zhao,

Zhang,

Wen

et al. 2023

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…In other words, the beta ratio of M3D SRAM cell can be adjusted without area penalty by changing the numbers of stacked MoS2 nanosheet FETs. The metal interconnect resistance increases significantly as technology node scales beyond 7nm node [1][2]. In order to release the impact of increased interconnect resistance, the metal line length of SRAM cell needs to be reduced.…”

Section: Stacked 2d Materials Fets M3d Sram Cellmentioning

confidence: 99%

“…The growing demand for AI applications is a major driver for reducing power and continued area scaling in SoCs (System-on-Chips). Continued scaling of the transistor and metal interconnection geometry is accompanied by the increased wire routing resistance which degrades the SRAM performance and array efficiency in advanced technology nodes [1][2]. The buried power SRAM [3] has been proposed to lower the bitline (BL) and wordline (WL) resistance and thereby enhances the write margin and performance even though the total capacitance per cell has been increased.…”

Section: Introductionmentioning

confidence: 99%