24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

Fundamental limits on the precision of in-memory architectures

“…Furthermore, we suggest that most IMCs today employ one or more of the following three in-memory compute models (see Fig. 5): (a) charge summing (QS) [7,14,15,40]; (b) current summing (IS) [12,16,17,30]; and (c) charge redistribution (QR) [1,7,15,33], and conjecture that these compute models are in some sense universal in that they represent an approximation to a 'complete set' of practical, i.e., realizable, mappings of variables from the algorithmic to the circuit domain as shown in Table 1.…”

Xor-Cim

“…For example, 8T XNOR design in [17] expanded 6T bit-cell into 8T bit-cell to support bitwise XNOR, achieving >50TOPS/W energy-efficiency for XNOR-Net [18]. It is realized that a higher precision is critical to maintain accuracy for large-scale dataset, thus SRAM-CIM macro for multi-bit inference is also demonstrated in silicon [10]. Moreover, on-chip training is also possible with SRAM based CIM architectures [19].…”

“…Compared to the 8T read-write decoupled SRAM [10], the dual-WL 6T SRAM is higher in density but suffers from two problems: read disturbance and input-dependent analog output shift. Read disturbance could be alleviated by lowering the WL access voltage during CIM mode and will be further suppressed by the one-side access nature of dual-WL 6T cell [27].…”

“…SRAM-CIM at 7nm provides higher density than 28nm RRAM-CIM (even with 4-bit per cell) [9]. The feasibility of SRAM based CIM accelerators has been proven in silicon prototype chips [10] [11] showing much more competitive energy efficiency compared to the digital ASIC designs (e.g. TPU [12] or Eyeriss [13]).…”

Benchmark of Ferroelectric Transistor-Based Hybrid Precision Synapse for Neural Network Accelerator

“…Nowadays, intensive research and development efforts have been focused on deep learning accelerators with CMOS and beyond-CMOS technologies [1]- [6]. To meet the requirement for data-centric computation, a new computing paradigm, compute-in-memory (CIM), has been proposed [7]- [10]. The emerging memory devices for binary memory applications are featured of high integration density, fast read and write speed, nonvolatility, good data retention, and reasonable endurance.…”