Benchmark of Ferroelectric Transistor-Based Hybrid Precision Synapse for Neural Network Accelerator

Luo, Yandong; Wang, Panni; Peng, Xiaochen; Sun, Xiaoyu; Yu, Shimeng

doi:10.1109/jxcdc.2019.2925061

Cited by 21 publications

(13 citation statements)

References 23 publications

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“…Recent experimental works have shown the ability to program FeFETs with voltage pulse widths as low as 50 ns (Jerry et al, 2018b) while the programming voltage can be brought down from 4 to 1.8 V by engineering the gate stack by adding an additional metal layer between the ferroelectric capacitor and MOS capacitor (Ni et al, 2019b). Table 2 shows a comparative study between FeFET-based analog synapse and various other candidates like PCM (Burr et al, 2010;Athmanathan et al, 2016;Ambrogio et al, 2018) and RRAM (Lee et al, 2012;Wu et al, 2017;Wu W. et al, 2018;Luo et al, 2019). One major benefit of using FeFET for implementing analog synapse is the reduced variability to less that 0.5% (Luo et al, 2019) and an order of magnitude reduction in write energy (Dünkel et al, 2018;Ni et al, 2019b).…”

Section: Discussionmentioning

confidence: 99%

“…Table 2 shows a comparative study between FeFET-based analog synapse and various other candidates like PCM (Burr et al, 2010;Athmanathan et al, 2016;Ambrogio et al, 2018) and RRAM (Lee et al, 2012;Wu et al, 2017;Wu W. et al, 2018;Luo et al, 2019). One major benefit of using FeFET for implementing analog synapse is the reduced variability to less that 0.5% (Luo et al, 2019) and an order of magnitude reduction in write energy (Dünkel et al, 2018;Ni et al, 2019b). The cell area is comparable to that of PCM and RRAM.…”

Section: Discussionmentioning

confidence: 99%

“…While a recent experiment on 60 μm 2 size FeFET devices exhibited 32 conductance states (equivalent to 5-bit precision) ( Jerry et al, 2018a , b ), in this work, we achieved eight non-overlapping conductance states (equivalent to 3 bits) in a 0.25 μm 2 size device. The precision of synaptic weight overed can be further improved by resorting to hybrid mechanisms like the recently proposed two transistor-one FEFET (2T1F) hybrid weight cell that allow up to 64 states with improved non-linearity and asymmetry factors ( Luo et al, 2019 ; Sun et al, 2019 ). Similar hybrid schemes have been applied to other novel devices like the three-transistor, one-capacitor, and two PCM (3T1C+2PCM) weight cell ( Ambrogio et al, 2018 ).…”

Section: Discussionmentioning

confidence: 99%

“…Specifically for achieving on-chip training, gradual and symmetric conductance update characteristic is extremely crucial. Recent research efforts have explored numerous potential candidates for building such analog synaptic weight cells including resistive random access memory (RRAM) ( Yu et al, 2015 ; Gao et al, 2015 ; Prezioso et al, 2015 ; Wu et al, 2017 ), phase-change memory (PCM) ( Kuzum et al, 2012 ; Burr et al, 2015 ; Ambrogio et al, 2018 ) and FeFETs ( Jerry et al, 2018a , 2019 ; Luo et al, 2019 ; Sun et al, 2019 ). In this work, we provide new experimental results of a FeFET-based synaptic weight cell at scaled device dimensions using 28 nm FeFET technology.…”

Section: Introductionmentioning

confidence: 99%

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Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

et al. 2020

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The two possible pathways toward artificial intelligence (AI)-(i) neuroscience-oriented neuromorphic computing [like spiking neural network (SNN)] and (ii) computer science driven machine learning (like deep learning) differ widely in their fundamental formalism and coding schemes (Pei et al., 2019). Deviating from traditional deep learning approach of relying on neuronal models with static nonlinearities, SNNs attempt to capture brainlike features like computation using spikes. This holds the promise of improving the energy efficiency of the computing platforms. In order to achieve a much higher areal and energy efficiency compared to today's hardware implementation of SNN, we need to go beyond the traditional route of relying on CMOS-based digital or mixed-signal neuronal circuits and segregation of computation and memory under the von Neumann architecture. Recently, ferroelectric field-effect transistors (FeFETs) are being explored as a promising alternative for building neuromorphic hardware by utilizing their nonvolatile nature and rich polarization switching dynamics. In this work, we propose an all FeFET-based SNN hardware that allows low-power spike-based information processing and co-localized memory and computing (a.k.a. in-memory computing). We experimentally demonstrate the essential neuronal and synaptic dynamics in a 28 nm high-K metal gate FeFET technology. Furthermore, drawing inspiration from the traditional machine learning approach of optimizing a cost function to adjust the synaptic weights, we implement a surrogate gradient (SG) learning algorithm on our SNN platform that allows us to perform supervised learning on MNIST dataset. As such, we provide a pathway toward building energy-efficient neuromorphic hardware that can support traditional machine learning algorithms. Finally, we undertake synergistic device-algorithm co-design by accounting for the impacts of device-level variation (stochasticity) and limited bit precision of on-chip synaptic weights (available analog states) on the classification accuracy.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

et al. 2020

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“…In this work, the voltage amplitude-based programming scheme is employed and thus the write voltage is swept to explore V TH . The swept write voltage ranges from 2.5 to 4.0 V, often used values in the literature (Jerry et al, 2017;Luo et al, 2019;Xiao et al, 2019), with a constant duration of 1 µs. As a final step, the explorations of V ML and write voltage are combined so that the mismatch level is equal to the number of activated synapses.…”

Section: All-in-memory Hamming Distance Computationmentioning

confidence: 99%

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

et al. 2022

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The separation of computing units and memory in the computer architecture mandates energy-intensive data transfers creating the von Neumann bottleneck. This bottleneck is exposed at the application level by the steady growth of IoT and data-centric deep learning algorithms demanding extraordinary throughput. On the hardware level, analog Processing-in-Memory (PiM) schemes are used to build platforms that eliminate the compute-memory gap to overcome the von Neumann bottleneck. PiM can be efficiently implemented with ferroelectric transistors (FeFET), an emerging non-volatile memory technology. However, PiM and FeFET are heavily impacted by process variation, especially in sub 14 nm technology nodes, reducing the reliability and thus inducing errors. Brain-inspired Hyperdimensional Computing (HDC) is robust against such errors. Further, it is able to learn from very little data cutting energy-intensive transfers. Hence, HDC, in combination with PiM, tackles the von Neumann bottleneck at both levels. Nevertheless, the analog nature of PiM schemes necessitates the conversion of results to digital, which is often not considered. Yet, the conversion introduces large overheads and diminishes the PiM efficiency. In this paper, we propose an all-in-memory scheme performing computation and conversion at once, utilizing programmable FeFET synapses to build the comparator used for the conversion. Our experimental setup is first calibrated against Intel 14 nm FinFET technology for both transistor electrical characteristics and variability. Then, a physics-based model of ferroelectric is included to realize the Fe-FinFETs. Using this setup, we analyze the circuit’s susceptibility to process variation, derive a comprehensive error probability model, and inject it into the inference algorithm of HDC. The robustness of HDC against noise and errors is able to withstand the high error probabilities with a loss of merely 0.3% inference accuracy.

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Compute in‐Memory with Non‐Volatile Elements for Neural Networks: A Review from a Co‐Design Perspective

et al. 2023

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Deep learning has become ubiquitous, touching daily lives across the globe. Today, traditional computer architectures are stressed to their limits in efficiently executing the growing complexity of data and models. Compute‐in‐memory (CIM) can potentially play an important role in developing efficient hardware solutions that reduce data movement from compute‐unit to memory, known as the von Neumann bottleneck. At its heart is a cross‐bar architecture with nodal non‐volatile‐memory elements that performs an analog multiply‐and‐accumulate operation, enabling the matrix‐vector‐multiplications repeatedly used in all neural network workloads. The memory materials can significantly influence final system‐level characteristics and chip performance, including speed, power, and classification accuracy. With an over‐arching co‐design viewpoint, this review assesses the use of cross‐bar based CIM for neural networks, connecting the material properties and the associated design constraints and demands to application, architecture, and performance. Both digital and analog memory are considered, assessing the status for training and inference, and providing metrics for the collective set of properties non‐volatile memory materials will need to demonstrate for a successful CIM technology.

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Benchmark of Ferroelectric Transistor-Based Hybrid Precision Synapse for Neural Network Accelerator

Cited by 21 publications

References 23 publications

Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges

All-in-Memory Brain-Inspired Computing Using FeFET Synapses

Compute in‐Memory with Non‐Volatile Elements for Neural Networks: A Review from a Co‐Design Perspective

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