25 ps/gate GaAs standard cell LSIs using 0.5 mu m gate MESFETs

Abstract

AhstractA design system of GaAs standard cell LSIs using 0.5ym MESFETs is presented in this report.This design system is intended to use to design LSIs which operating speed is from several hundred MHz to several GHz. A basic gate is DCFL, and the delay time is less than 25ps. The library includes 40 cells and 8 1/0 buffers which are designed to be compatible with ECLlOK, TTL, CMOS, and GaAs. Using this design system, an LSI is fabricated and its performances are evaluated. The results of evaluation show that the error in post-layout simulation is under 10%.High speed GaAs semi-custom LSIs are promising devices on various communication and information systems. Generally, there are two ways to develop semi-custom LSIs, with standard cells or gate arrays[l-31. The standard cell LSIs have advantages to operate with high speed and to reduce chip size compared with the gate array LsIs, because the standard cell LSIs are able to be built up with smaller redundancy of routing. We developed a design system of GaAs standard cell LSIs.This paper describes the design of basic logic gates, cells and layout, a delay model, and the evaluation of the system performances.of This system is intend to design LSIs which operates from several hundred MHz to several GHz. A 0.5pm gate MESFET is used as basic device to realize high speed operation. The basic logic gate is chosen DCFL (Rirect Coupled EET Logic) because of its simple circuitry and low power dissipation. D-FET gate width is designed 3pm. That is minimum size without the narrow channel effect. E-FET gate width is designed 9pm suiting with D-FET current. In order to realize stable operation of the GaAs standard cell LSI which operating speed is several hundred MKz or more, the ability of basic gate is required as follows.(1) The delay of basic gate is less(2) The noise margin is larger than than 30ps.SOmV.Device parameters are optimized to satisfy these requirements in a wide temperature range.The delay of DCFL gates (Tpd) mainly depends on saturation current (Idss) of the load FET (D-FET) of DCFL. Fig.1 shows the measured dependence of Tpd on Idss.Idss of D-FET is decided 3 0 0 U at room temperature ( 2 5 "~) to satisfy the required Tpd, considering the margin of the variations based on fabrication process and temperature characteristics. Next, the noise margin (NM) of DCFL gate is examined. NM mainly depends on Idss of D-FET, the threshold voltage (Vth) of the switching FET (E-FET) of DCFL and K-value of E-FET.Idss of D-FET has been fixed as mentioned above. K-value and Vth of E-FET are mutually correlated as shown in Fig.2. Therefore, to obtain sufficient NM, Vth of E-FET is optimized. Fig. 3 shows simulated dependence of NM of DCFL inverter on Vth of E-FET. The most stable value of E-FET Vth is lOOmV at 25-c. Fig.4 and Fig.5 show the measured temperature characteristics of the delay of the basic gate and that of NM, respectively. In the temperature range between -4O"c and 75"c, the delay time of DCFL inverter can be kept below 25ps, and the NM is larger than 80mV. 0.2 0 ...