256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers

Kang, Dong‐Ku; Jeong, Won-Ki; Kim, Chulbum; Kim, Doo-Hyun; Cho, Yong Sung; Kang, Kyung‐Tae; Ryu, Jiseon; Kang, Kyung-Min; Lee, SungYeon; Kim, Wandong; Lee, Hanjun; Yu, Jaedoeg; Choi, Na-Young; Jang, Dong-Hoon; Lee, Cheon An; Min, Young-Sun; Kim, Moo-Sung; Park, An-Soo; Son, Jooyoung; Kim, In-Mo; Kwak, Pansuk; Jung, Bongjin; Lee, Doo-Sub; Kim, Hyung-Gon; Ihm, Jeong-Don; Byeon, Dae–Seok; Lee, Jin-Yup; Park, Kitae; Kyung, Kye-Hyun

doi:10.1109/jssc.2016.2604297

Cited by 87 publications

(42 citation statements)

References 2 publications

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“…Such a device was shown to exhibit superior performance with respect to a conventional vertical nanowire transistor, because of the high defectivity in the central region that plagued the performance of the latter structure. The gate stack of today's 3D NAND can be based on either a floating gate [23,[287][288][289][290][291], similar to planar NAND devices, or a charge-trap stack similar to an oxide/nitride/oxide (ONO) layer, where the charge is stored in traps within the nitride layer [10,11,22,292].…”

Section: D Nand Reliabilitymentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: D Nand Reliabilitymentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…Another highlight of the second generation V-NAND is the so-called single-sequence programming.In this improved algorithm, the V-NAND asks for 3 NAND Flash pages at the start of the programming, and it writes the pages at once, turning into faster operations and lower power consumption. The third generation of V-NAND architecture became public in 2016 [13]. It is still a three bits/cell architecture, but this time, it is a 256-Gb product based on a stack of 48 layers.…”

Section: V-nand Architecturementioning

confidence: 99%

“…In the second category, we will provide the description of several architectures like: the Bit Cost Scalable (BiCS) presented for the first time by Toshiba [8,9], its improved version, namely the Pipe-shaped Bit Cost Scalable (P-BiCS) [10,11], and the pathway to the V-NAND architecture from Samsung [12,13] ranging from the Vertical Recess Array Transistor (VRAT) [14], the Vertical Stacked Array Transistor (VSAT) [15], and the Terabit Cell Array Transistor (TCAT) [16].…”

Section: Introductionmentioning

confidence: 99%

Architectural and Integration Options for 3D NAND Flash Memories

Micheloni

Crippa²,

Zambelli

et al. 2017

Computers

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Nowadays, NAND Flash technology is everywhere, since it is the core of the code and data storage in mobile and embedded applications; moreover, its market share is exploding with Solid-State-Drives (SSDs), which are replacing Hard Disk Drives (HDDs) in consumer and enterprise scenarios. To keep the evolutionary pace of the technology, NAND Flash must scale aggressively in terms of bit cost. When approaching ultra-scaled technologies, planar NAND is hitting a wall: both academia researchers and industry worked to cope with this issue for several decades. Then, the 3D integration approach turned out to be the definitive alternative by eventually reaching mass production. This review paper exposes several 3D NAND Flash memory technologies, along with their related integration challenges, by showing their different layouts, scaling trends and performance/reliability features.

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“…Compared to the previous generation, there hasn't been macroscopic changes in the memory cell itself, but it is worth mentioning that the number of control gate layers is 32 instead of the previous 24. [17,20,25,27] The other highlight of this device is the Single-Sequence Programming operation. TLC functionality (i.e.…”

Section: V-nandmentioning

confidence: 99%

“…V-NAND Gen3 becomes public at the IEEE International Solid State Circuits Conference (ISSCC) in 2016 [27]. It is again a TLC device, but this time it is a 256 Gb based on a vertical stack of 48 control gate layers.…”

Section: V-nandmentioning

confidence: 99%