26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2&amp;#x00D7; time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS

Sung, Barosaim; Jo, Dong‐Shin; Jang, Il-Hoon; Lee, Dong-Suk; You, Yong-Sang; Lee, Yong-hee; Park, Ho‐Jin; Ryu, Seung‐Tak

doi:10.1109/isscc.2015.7063127

Cited by 33 publications

(10 citation statements)

References 5 publications

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“…For example, a subranging flash SAR ADC has been described in [22], which resolves the MSBs with a flash ADC that controls the MSB capacitors of the CDAC in the SAR ADC of the second stage to resolve the remaining LSBs. Some low-power hybrid ADC architectures have recently been introduced, combining methods of subranging and time-interleaving with flash and SAR stages [29][30][31]. A subranging TI-ADC has been reported in [29], which uses a front-end flash ADC to resolve the MSBs at the full conversion rate of 1 GS/s.…”

Section: Power-efficient High-speed Medium-resolution Adcsmentioning

confidence: 99%

“…Redundancy in the flash ADC and the CDAC is used to relax the offset constraints of the flash ADC. In [30], two flash TI-SAR ADCs are time-interleaved to lower the sampling rate of the front-end flash in order to save more power compared to [29]. It is worthwhile to mention that for these architectures, the mismatches between the two subranging stages must be reconciled through calibration or redundancy techniques to avoid linearity problems.…”

Section: Power-efficient High-speed Medium-resolution Adcsmentioning

confidence: 99%

“…In particular, since each SHDAC is shared by the flash ADC and the CABS ADC, it is ensured that an identical sampled voltage is processed by both stages. In comparison to hybrid ADC architectures in which the signal is sampled separately for the MSB stage and the LSB stage [30], this architecture is more immune to the sampling errors that originate from clock skews and resistor-capacitor (RC) mismatches between the two stages. However, it requires additional bootstrap switches to connect the flash ADC to the proper SHDAC during each sampling cycle.…”

Section: Architecture Case Studymentioning

confidence: 99%

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Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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This article reviews design challenges for low-power CMOS high-speed analog-to-digital converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding ADCs, subranging and two-step ADCs, pipelined ADCs, successive approximation ADCs) are described with particular focus on their suitability for the construction of power-efficient hybrid ADCs. The overview includes discussions of channel offsets and gain mismatches, timing skews, channel bandwidth mismatches, and other considerations for low-power hybrid ADC design. As an example, a hybrid ADC architecture is introduced for applications requiring 1 GS/s with 6-8 bit resolution and power consumption below 11 mW. The hybrid ADC was fabricated in 130-nm CMOS technology, and has a subranging architecture with a 3-bit flash ADC as a first stage, and a 5-bit four-channel time-interleaved comparator-based asynchronous binary search (CABS) ADC as a second stage. Testing considerations and chip measurements results are summarized to demonstrate its low-power characteristics.

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Section: Power-efficient High-speed Medium-resolution Adcsmentioning

confidence: 99%

Section: Power-efficient High-speed Medium-resolution Adcsmentioning

confidence: 99%

Section: Architecture Case Studymentioning

confidence: 99%

See 1 more Smart Citation

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Zahrai

Onabajo

2018

JLPEA

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“…As shown in Fig.7, a differential clock buffer is used to match impedance and clock reshaping with no additional jitter issue. Then the 8 Divider block produce 8 no-overlap clock Clk (0) to Clk (7) . To minimize the systematic mismatches in the clock path, an H-tree block is used to route clocks.…”

Section: Figmentioning

confidence: 99%

A 10-bit 1.2 GS/s 45 mW time-interleaved SAR ADC with background calibration

Pu-Jie

et al. 2018

IEICE Electron. Express

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A 10-bit 1.2GS/s power efficient time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) is present in this paper. Substrate bias effect depression and output resistance stabilization techniques are provided to enhance the linearity of input buffer. Further, meta-stability restrained trigger comparator is used to enhance the ENOB (effective number of bits) of SAR ADC. Additionally, a digital background calibration technique is proposed to suppress the inter-channel gain, offset and timing skew mismatches. To demonstrate the proposed techniques, a design of time-interleaved SAR ADC is fabricated in 55-nm CMOS technology, consuming 45mW from 1.2V power supply with a SNDR of 50dB and SFDR of 60dB. The proposed ADC core occupies an active area of 0.84mm 2 , and the corresponding FoM is 145 fJ/conversion-step with Nyquist rate. Keywords: Analog-to-digital converter (ADC), Time-interleaved ADC, successive-approximation-register (SAR) ADC, Meta-stability restrained, High-linearity, Background calibration. Classification: Analog integrated circuits [11] Sunghyuk Lee, Anantha P. Chandrakasan and Hae-Seung Lee, "A 1GS/s 10b 18.9mW time-Interleaved SAR ADC with background timing skew calibration", IEEE J.

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“…A 500 fF small capacitor is used instead of the capacitor DAC (CDAC) as the sampling capacitor to get high input signal bandwidth and reduce the loading of input buffer. Additional, the bottom-plate sampling is utilized to ensure the linearity of the sampling [5]. The sampling instances of TI channels are synchronized with the same master clock È m , which is selectively applied to each channels via an MUX controlled by the clock signals en1 to en8 .…”

Section: Proposed Adc Architecturementioning

confidence: 99%

A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS

Zhu

Zhou

et al. 2017

IEICE Electron. Express

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This paper presents an 8-channel time-interleaved SAR ADC. A novel sampling structure is proposed to improve the input bandwidth which also avoids time-skew calibration. The comparator offset cancellation is achieved by body voltage adjustment using low-power charge pump. Each channel has its own on-chip reference buffer to stable reference voltage and correct gain mismatches. The prototype is fabricated in 1P6M 0.13 µm CMOS technology. At 400 MS/s, the ADC achieves an SNDR of 50.84 dB and 45.7 dB at 19.1 MHz and 451 MHz, respectively. It consumes 200 mW, resulting in FOM of 1.76 pJ/con-step.

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26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS

Cited by 33 publications

References 5 publications

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

Review of Analog-To-Digital Conversion Characteristics and Design Considerations for the Creation of Power-Efficient Hybrid Data Converters

A 10-bit 1.2 GS/s 45 mW time-interleaved SAR ADC with background calibration

A 400-MS/s 10-b 8 interleaved SAR ADC in 0.13 um CMOS

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