266–2133 MHz phase shifter using all‐digital delay‐locked loop and triangular‐modulated phase interpolator for LPDDR4X interface

Abstract

A 266-2133 MHz phase shifter is proposed for LPDDR4X interface, utilising an all-digital delay-locked loop (DLL) and a triangular-modulated phase interpolator (PI) to improve the jitter and linearity. The DLL consists of two kinds of DLLs: a global DLL to assist fast locking; and a local DLL which uses an adaptive-window phase detector and a folded delay line to reduce jitter and improve linearity. The PI uses a triangular-modulated clock waveform to achieve good linearity over a wide frequency range. The prototype chip is implemented in a 65 nm CMOS process. The measured jitter of the DLL is 3.08 ps rms /19.93 ps pp at 2133 MHz. The measured differential non-linearity of the phase shifter is <0.91 LSB at 2133 MHz, and the power efficiency is about 2.7 mW/GHz.

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process

“…The simulation results indicate that the operating frequency range is improved but the cost is increased power consumption. Global deskew DLLs are based on TDCs for phase detection which are able to provide fast locking [14][15], but they have high area and power consumption.…”

Orthogonal phase mixing for improved linearity phase interpolator

“…PI, as the name suggests, interpolates the phase between two reference clocks by mixing them with varying proportions. Figure 1 shows one of the common ways to implement phase interpolator using contenting invertors [2]. The mixing ratio between reference clocks can be linear [1], trigonometric [1], and non-linear [3,4] to achieve more linear phase steps.…”