266-nm ps Laser Ablation for Copper-Plated p-Type Selective Emitter PERC Silicon Solar Cells

Challenges facing copper‐plated metallisation for silicon photovoltaics: Insights from integrated circuit technology development

“…One approach to reducing contact recombination is to use a SE, where the surface under the metal contact is more heavily‐doped . Copper‐plated metallisation has been demonstrated with solderable p‐type SE PERC cells; however, achievement of the SE required additional patterning steps to either form the SE or form anchor points in laser‐doped regions to provide sufficient adhesion for soldered interconnection …”

“…For example, Ni silicides and Ag crystallites may extend non‐uniformly into the Si from the metal surface for plated and screen‐printed cells, respectively. For plated cells, depending on the thermal conditions used for silicide formation, Ni can penetrate some distance from the surface and may impact the pFF of the device through increased non‐ideal recombination . Figure shows a TEM image of a silicide formed after sintering a Ni layer (which had been deposited using LIP) for 10 minutes at 450°C.…”

“…Although the use of a UV ps laser has provided a method for forming adherent Cu‐plated grids on Si solar cells, some concerns remain regarding variability in the process. Hsiao et al reported that the 180° busbar pull force measured for some p‐type PERC cells could be as high as that measured for comparative screen‐printed cells, but measurements on similarly‐processed cells could be very low and insufficient for soldering . They identified that Ni silicides (Ni 2 Si and NiSi) could be detected in cells for which a strong pull force was measured but was absent in cells with a very low pull force.…”

“…Although the number of processing steps can be reduced by annealing after all plating steps have been performed (see Figure 22), the simpler process allows for less control over the silicide formation than possible with the process used by BP Solar (see Figure ). However, very little analysis and optimisation have been performed with regard to the formation of Ni silicides in the presence of an overlying Cu/Ag stack and the results of Hsiao et al would suggest that it may be timely to investigate how the Ni silicide phases form for different surface pre‐treatments and annealing conditions, and correlate these findings with contact adhesion for both busbars and fingers.…”

“…Whereas Cu electroplating of interconnects for earlier IC devices involved trench (blind via) conformal plating using damascene chemistry, bottom‐up plating approaches are being developed for the high aspect ratio TSVs required for 3D‐IC applications (see Figure ). Bottom‐up plating makes it easier to achieve void‐free interconnectors and allows higher aspect ratio structures to be formed . It can also reduce the overburden, hence Cu wastage and CMP time and allow the use of through‐wafer (one‐side) plating …”