28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter

Design Considerations of Data Converters for Industrial Technology

“…This work utilizes highly efficient charge-redistribution SAR ADC to counteract the disadvantages of the conventional ΣΔ ADC, which is a typical hybrid architecture ADC design [9]. Nowadays, many noise shaping SAR ADC have appeared on the top journals and top conferences in the field of microelectronics, for instance, an ultra-low power 0.46 mW noise-shaping SAR ADC with 5MHz Bandwidth and 79.7 dB-SNDR incorporating a dynamic-amplifier-based FIR-IIR filter has been published in 2017 IEEE International Solid-State Circuits Conference (ISSCC) [10]; A low power 2.4-mW 300-MS/s passive noise shaping SAR ADC with 25-MHz Bandwidth [11] and a 4.2 mW 10MHz BW 74.4 dB SNDR fourth-order CT DSM with second-order digital noise coupling utilizing an 8b SAR ADC [12] have been published in 2017 Symposium on VLSI Circuits; Furthermore, an 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier has been designed [13]. In a conclusion, noise shaping SAR ADCs have become research focus over the years [14].…”

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications

“…Alternatively, this long conversion time could be effectively reduced by utilizing the pipeline operation at the cost of area and power [16], [17]. In addition, oversampling SAR ADCs [18] and noise-shaping SAR ADCs [19] have been reported to give shorter conversion times and higher resolution, but their achieved resolutions are still limited.…”

Dither‐based background calibration of capacitor mismatch and gain error in pipelined noise shaping successive approximation register ADCs

“…Introduction: The noise-shaping successive approximation register ADC (NS SAR ADC) combines the advantages of SAR ADC and ΣΔ ADC, simultaneously achieving low power consumption and high resolution, but with the limited bandwidth of <5 MHz [1][2][3]. To extend the bandwidth, the pipelined operation was added to NS SAR ADC in [4].…”

“…The ditherbased background calibration was implemented to correct a gain error in pipeline-SAR ADCs [5,6], but it required complex logic to detect the conditions of injecting the dither signal or is not effective when capacitor mismatch appears simultaneously. Data-weighted averaging (DWA) logic was adopted to dissipate harmonics caused by capacitor mismatch in the NS SAR ADCs [3,7], but cannot correct the gain error.…”