Dither‐based background calibration of capacitor mismatch and gain error in pipelined noise shaping successive approximation register ADCs

Abstract

A dither-based background calibration with data-weighted averaging logic to correct capacitor mismatch and inter-stage gain error in pipelined noise shaping successive approximation register ADCs is proposed. By injecting the dither signal in the background, the interstage gain is obtained. Besides, the data-weighted averaging logic is adopted to dissipate harmonics caused by the mismatch of capacitors. Owing to the effective combination of the two methods, there is no need to detect the conditions of injecting the dither signal. As a result, the calibration requires simple logic and adds little analogue overhead.

Low Power SAR ADC Design with Digital Background Calibration Algorithm

“…To correct the capacitor mismatch, Ref. [6] proposed a dither-based background calibration technique with a data-weighted averaging method but required extra circuits. Ref.…”

Background calibration of bit weights in pipeline ADCs using a counteracting dither technique

“…Introduction: Bit-weight error, caused by capacitor mismatch and inter-stage gain error, significantly deteriorates the linearity of pipeline analogue-to-digital converters (ADCs) [1]. Correlation-based algorithms, with comparator dither or digital-to-analogue-converter (DAC) dither, obtain the bit weights and remove their errors in the background with small overheads [1][2][3][4]. However, both comparator and DAC dither injections cause an obvious residue swing increment at the amplifier output, which occupies the redundancy range, leads to higher-order non-linearities, or even saturates the back-end ADC [5][6][7].…”

“…Then, W 1 can be acquired by (4) and (5). Finally, all the bit weights are obtained and used to calculate the final output D out .…”

Digital background calibration technique for pipelined SAR ADCs with detect‐and‐switching algorithm

“…However, in pipelined SAR ADCs, the capacitor mismatch and inter-stage gain error solicit significant deterioration of dynamic performance. To mitigate the mentioned issue and obtain a high resolution above 12 bits, dynamic linearisation techniques [1][2][3][4][5] are usually required. Data-weighted averaging (DWA) [1,2] is a common technique to remedy the capacitor mismatch in oversampling SAR ADC category, but at the expense of increased timing slots and extra hardware overhead due to the extra DWA logic.…”

“…However, the dithering-like feedback signal occupies part of the signal range and consumes system dynamic range (DR). Besides, dithering-based calibration technique [3][4][5] can correct capacitor mismatch combined with a gain error or pure capacitor mismatch in the background while mitigating the residueswing problem caused by the dithering signal. Nevertheless, in [3,4], they either require complex logic to determine whether to inject random dithering or increase the swing of inter-stage amplifier in pipelined SAR ADCs.…”