Background calibration of bit weights in pipeline ADCs using a counteracting dither technique

Abstract

A counteracting dither technique is proposed to remedy the bit-weight error issue in pipeline analogue-to-digital converters (ADCs). A capacitor is added to the traditional comparator dither scheme. By switching the added capacitor, the residue swing increment due to comparator dither is counteracted, thereby greatly relaxing the design requirement of the residue amplifier. Behaviour-level simulation results show that the spurious-free-dynamic-range and the signal-tonoise-and-distortion-ratio are improved from 59 and 52.8 dB to 102.7 and 85 dB after calibration in a 14-bit ADC, respectively.

An interstage gain calibration technique for pipelined ADCs exploiting complementary dithering and calibration windows detector

“…A higher 𝜇 leads to a swifter convergence but lower calibration precision and vice versa. [18,19,21] employed two-fold comparators to screening the input signal range affected solely by the injection of DAC dither. However, this scheme not only results in increased power consumption but also diminishes the sampling linearity.…”

“…Notwithstanding, the complexity of the analog circuits is evidently increased by injecting the dither through the addition of two comparators and the division of the unit capacitor into two within each 1.5-bit stage. Furthermore, the use of twice the number of comparators to counter the increment of residual amplitude not only eventuates in significant power consumption but also dilutes the sampling linearity [18,19,20].…”

A Multi-Dimensional Calibration Based on Genetic Algorithm in a 12-Bit 750 MS/s Pipelined ADC

“…The common compensation method of pipelined ADCs is based on the weight of the bit [ 21 , 23 , 24 ]. This can be summarized using the following expression: …”