28-GHz CMOS Power Amplifier Linearized With Resistive Drain-Body Connection

Cho, Gwangsik; Jeong, Gwanghyeon; Hong, Songcheol

doi:10.1109/lmwc.2020.3015216

Cited by 12 publications

(2 citation statements)

References 6 publications

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“…In addition to the memory effect, the nonlinear capacitance gate-to-drain capacitances (C GD ) and drain-to-source capacitances (C DS ) of power transistors is also one of the reasons for the poor linearity of RF CMOS PA [53]. For further improving linearity, G. Cho et al proposed a simple but effective resistive body network, reducing the gate capacitance changes of the power transistor [54] (see Figure 9b). As a result, the presented PA, composed of 2-stage differential cascode, achieves linearity PAE of 25% at output power of 20.25 dBm at 28 GHz.…”

Section: Cascodementioning

confidence: 99%

Review of Ka-Band Power Amplifier

Wang

et al. 2022

Electronics

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With the increase in the demand for high-speed transmission communication, satellite communication is developing rapidly. Because of the bandwidth capacity, the K/Ka band is considered the mainstream frequency band of satellite communication. The performance of a power amplifier (PA) directly affects the power of the transmitter, so the application of a power amplifier in Ka-band satellite communication is very important. A review of the state-of-the-art PA in the Ka band is presented in this article. The structure of the PA introduced includes common source, cascode, stacked field-effect transistor (FET), power combining, and Doherty PA, highlighting the advantages and disadvantages. The main solid-state technologies are outlined, including Si, SiGe, GaAs, and GaN, emphasizing Si complementary metal–oxide–semiconductor (CMOS) due to low price and high integration.

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Section: Cascodementioning

confidence: 99%

Review of Ka-Band Power Amplifier

Wang

et al. 2022

Electronics

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“…More recently, studies have been underway to configure single-chip transceivers by utilizing high-integrity characteristics of CMOS [3][4][5]. However, it may not communicate smoothly if the transceiver path lacks gain, which is calculated to determine the appropriate margin when performing link budget analysis.…”

Section: Introductionmentioning

confidence: 99%

Optimization Technique for High-Gain CMOS Power Amplifier for 5G Applications

et al. 2021

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In this study, a differential power amplifier (PA) with a high gain of over 30 dB by configuring a three-stage common source unit amplifier was designed. To ensure the stability of the high-gain differential PA, the analysis to apply the capacitive neutralization method to the differential common source PA was conducted. From the analysis, the required neutralized capacitance was quantitatively calculated from the estimated parasitic components of a power cell used in the PA. To verify the feasibility of the proposed optimization technique, a Ka-band PA was designed with a 65 nm RFCMOS process. The measurement results showed a gain of 30.7 dB. The saturated output power was measured as 16.1 dBm, maximum power-added efficiency (PAE) was 29.7%, and P1dB was 13.1 dBm.

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