280-GHz schottky diode detector in 130-nm digital CMOS

Han, Ruonan; Zhang, Yaming; Coquillat, Dominique; Hoy, Julie; Videlier, H.; Knap, W.; Brown, E. R.; O, Kenneth K.

doi:10.1109/cicc.2010.5617387

Cited by 45 publications

(50 citation statements)

References 8 publications

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“…26, where an incoherent source is employed to illuminate the object. The integrated on-chip Dicke switch eliminates the need for lock-in amplifier and mechanical chopping system used in previously reported silicon-based imaging tests [17], [38]. The reason of using an active imaging setup is because the loss introduced by the on-chip antenna degrades the system NETD.…”

Section: System Measurementsmentioning

confidence: 97%

A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

Chen

Wang

Yao

et al. 2012

IEEE J. Solid-State Circuits

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This paper presents a W-band 2 2 focal-plane array (FPA) for passive millimeter-wave imaging in a standard 0.18 m SiGe BiCMOS process ( GHz). The FPA incorporates four Dicke-type receivers representing four imaging pixels. Each receiver employs the direct-conversion architecture consisting of an on-chip slot folded dipole antenna, an SPDT switch, a low noise amplifier, a single-balanced mixer, an injection-locked frequency tripler (ILFT), an IF variable gain amplifier, a power detector, an active bandpass filter and a synchronous demodulator. The LO signal is generated by a shared Ka-band PLL and distributed symmetrically to four local ILFTs. The measured LO phase noise is at 1 MHz offset from the 96 GHz carrier. This imaging receiver (without antenna) achieves a measured average responsivity and noise equivalent power of 285 MV/W and 8.1 , respectively, across the 86-106 GHz bandwidth, which results a calculated NETD of 0.48 K with a 30 ms integration time. The system NETD increases to 3 K with on-chip antenna due to its low efficiency at W-band. MMW images have been generated in transmission mode. This work demonstrates the highest integration level of any silicon-based systems in the 94 GHz imaging band.

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Section: System Measurementsmentioning

confidence: 97%

A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

Chen

Wang

Yao

et al. 2012

IEEE J. Solid-State Circuits

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“…The series resistance is R s , junction capacitance is C j and R j represents the dynamic resistance (1/g m ) of diode. NEP of the diode detector with modulation frequency higher than the 1/f noise corner frequency is denoted [7,12] NEP…”

Section: Direct Conversion With Schottky-barrier Diodementioning

confidence: 99%

“…For example, Excellent NEP performance for III-V semiconductor SBD has been reported in [6] (20 pW/Hz at 800 GHz). A Shallow Trench Separated (STS) Schottky barrier diode with 1.5 THz cut-off frequency can be fabricated in 130 nm digital CMOS [7]. Other than the direct-conversion receiver with SBD, the recent superregenerative receiver (SRX) is also explored [8] with high sensitivity, which is optimum for mm-wave imaging [9].…”

Section: Introductionmentioning

confidence: 99%

A high-sensitivity 135GHz millimeter-wave imager by compact split-ring-resonator in 65-nm CMOS

Yang

et al. 2015

Solid-State Electronics

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“…In normal usage, the output current will drive a load resistor or a large charge-storage capacitor. The -curves of a Schottky diode reported in [22] is compared with a conventional diode-connected low-nMOS transistor and various IPVM-driven low-nMOS transistors. The Schottky diode has an mV nA.…”

Section: In-phase Gate-boosting Rectifiermentioning

confidence: 99%

A Millimeter-Wave In-Phase Gate-Boosting Rectifier

Wang

Liao

Tsai

et al. 2014

IEEE Trans. Microwave Theory Techn.

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This paper introduces a new class of RF-to-dc rectifiers called the in-phase gate-boosting rectifier (IGR). An IGR utilizes an in-phase passive voltage multiplier (IPVM) to boost in-phase swing from the driving swing. This design simultaneously reduces the effective threshold voltage, forward resistance, and the reverse leakage current of the rectifying transistor. As a consequence, the sensitivity and the efficiency of a high-frequency rectifier can be improved. Furthermore, a -loaded IPVM presents low input conductance and is shunted with the drains/sources of the rectifying transistors. This makes the realization of the input matching network between the IGR core and the antenna easier, and achieves a higher voltage swing at the input terminals of the IGR core. The criteria, properties, and relating proofs of the IPVM are also discussed. A differential seven-stage millimeter-wave IGR is implemented in a 65-nm RF CMOS process. In this design, an interleaving internal threshold cancellation bias scheme is also introduced to further suppress the power consumption due to biasing circuitry without increasing the layout area. The implemented integrated circuit achieves a state-of-the-art 7-dBm sensitivity with 20% peak efficiency at 53 GHz and a bandwidth of 10 GHz from 46 to 56 GHz. Index Terms-Energy harvesting, rectifying circuits. 0018-9480

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280-GHz schottky diode detector in 130-nm digital CMOS

Cited by 45 publications

References 8 publications

A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna

A high-sensitivity 135GHz millimeter-wave imager by compact split-ring-resonator in 65-nm CMOS

A Millimeter-Wave In-Phase Gate-Boosting Rectifier

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