2D Semiconductor FETs—Projections and Design for Sub-10 nm VLSI

Cao, Wei; Kang, Jiahao; Sarkar, Deblina; Liu, Wei; Banerjee, Kaustav

doi:10.1109/ted.2015.2443039

Cited by 270 publications

(192 citation statements)

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“…Compounds based on Mo and W are the bestknown examples of semiconduct ing TMDCs. In their single and fewlayer form they show many attractive features such as atomicscale thickness and large band gaps (1-2 eV), leading to a high degree of electrostatic control 11 and scalability for nanoscale transistors 12 , exquisite sensing capabili ties 13 , high breakdown voltages 14 , tunable optical properties 8,9,[15][16][17] , a high degree of mechanical flexibility 18 and the possibility of engi neering new materials through the realization of van der Waals hetero structures 19 . Other semiconducting 2D materials such as phosphorene 20 and silicene 21 are also attracting growing interest.…”

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confidence: 99%

Electrical contacts to two-dimensional semiconductors

et al. 2015

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Semiconducting electronic devices utilize fine control over the flow of charge carriers, which are injected into the semi conducting material through electrical contacts. The quality of the electrical contacts -quantified through contact resistance -is as important to the proper functioning of the entire device as the semiconductor (SC) itself. Since the early 1990s, researchers have explored a wide variety of electronic devices based on nanostruc tures with different dimensionalities, ranging from one dimensional (1D 20 and silicene 21 are also attracting growing interest. One of the most common electronic devices, in both the research and industrial environments, is the fieldeffect transistor (FET). Low contact resistance in 2D SCbased devices is critical for achiev ing high 'on' current, large photoresponse 22 and highfrequency operation 23 . However, the major issue for 2D SC FET transistors is the existence of a large contact resistance at the interface between the 2D SC and any bulk (or 3D) metal, which drastically restrains the drain current [24][25][26] . Contacting 2D SCs presents a certain number of experimental and conceptual challenges. The theoretical concepts that underlie our understanding of conventional metal-SC contacts break down in the limit where the SC thickness is smaller than the The performance of electronic and optoelectronic devices based on two-dimensional layered crystals, including graphene, semiconductors of the transition metal dichalcogenide family such as molybdenum disulphide (MoS 2 ) and tungsten diselenide (WSe 2 ), as well as other emerging two-dimensional semiconductors such as atomically thin black phosphorus, is significantly affected by the electrical contacts that connect these materials with external circuitry. Here, we present a comprehensive treatment of the physics of such interfaces at the contact region and discuss recent progress towards realizing optimal contacts for two-dimensional materials. We also discuss the requirements that must be fulfilled to realize efficient spin injection in transition metal dichalcogenides. depletion and transfer lengths. In the 2D limit, the properties of the interface -the chemical interaction between the metal and the SC -govern everything. Substitutional doping, a common strat egy adopted to decrease the contact resistance in bulk SCs, is not applicable here because it would modify both the 2D material and its properties. In addition, the pristine surface (that is, no dangling bonds) of a 2D material makes it difficult to form strong interface bonds with a metal, thereby increasing contact resistance.The quantum limit to the contact resistance (R C min ) is determined by the number of conducting modes within the SC channel 27,28 , which is connected to the 2D charge carrier density (n 2D ), yielding R C min = h/(2e 2 k F ) = 0.026/√n 2D ≈ 30 Ω μm at n 2D = 10 13 cm -2 (ref. 29) -a value three orders of magnitude below the typical contact resist ance to monolayer MoS 2 . Here, h is Planck's constant, k F is the Fermi wavevector a...

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Electrical contacts to two-dimensional semiconductors

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“…Here, the material parameters such as lattice constant, effective masses and band-gaps are taken from literature3031323334 and reported in Table 1. This approach has been widely used to project performance of nanoscale transistors based on Si, III-V41 and now 2D materials11121314. Further, to model Schottky contacts, we extend our Hamiltonian at the contacts for the zero-bandgap metal and applied Dirichlet boundary conditions.…”

Section: Methodsmentioning

confidence: 99%

“…Amongst the other remarkable features of TMDCs, their layered structure provides 2D films of controllable uniform thickness with dangling-bonds free interfaces. Moreover, their extreme thinness and low in-plane dielectric constant alleviate short-channel effects (SCE) and drain-induced-barrier-lowering (DIBL)1112, which are detrimental to device performances. The high effective mass of charge carriers (especially with respect to III-V materials) helps reducing direct source-to-drain tunneling at ultra-scaled dimensions1314, providing a better control of the device OFF-state by the gate terminals.…”

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“…Moreover, the device switching properties become more expressive, as each device is now acting as a comparison-driven switch and will allow the realization of compact logic gates, thus improving the computational density in 2D-flatronics2324. However, to date, scaling opportunities with 2D materials have been theoretically explored only in unipolar, physically-doped devices, with Ohmic contacts1112131425. This has been done disregarding the great difficulties that the accurate and controlled doping of the material brings to the fabrication process, i.e., doping is already one of the major sources of variability in silicon CMOS devices26, and that achieving Ohmic contact to 2D materials has, so far, proven to be a challenging task.…”

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Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs

Resta

Agarwal

Lin

et al. 2017

Sci Rep

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Two-dimensional semiconducting materials of the transition-metal-dichalcogenide family, such as MoS2 and WSe2, have been intensively investigated in the past few years, and are considered as viable candidates for next-generation electronic devices. In this paper, for the first time, we study scaling trends and evaluate the performances of polarity-controllable devices realized with undoped mono- and bi-layer 2D materials. Using ballistic self-consistent quantum simulations, it is shown that, with the suitable channel material, such polarity-controllable technology can scale down to 5 nm gate lengths, while showing performances comparable to the ones of unipolar, physically-doped 2D electronic devices.

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“…Applying gate voltage (1 V) the barrier is reduced hence the electrons flow from source to drain. Since the effective channel length increases with increasing underlap Length, introducing series resistance in the underlap length region that reduces SS for shorter gate length [20]. Thus the short channel effects getting reduced by reducing coupling capacitance.…”

Section: Parameter Name Valuementioning

confidence: 99%

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

Faisal¹,

Hasan²,

Hossain³

et al. 2017

CCS Archive

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GaN-based double gate metal-oxide semiconductor fieldeffect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green's function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, V GS =1 V while it is going to off at V GS = 0 V. The ON-state and OFFstate drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, V DS = 0.75 V. The subthreshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (L UN ). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

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2D Semiconductor FETs—Projections and Design for Sub-10 nm VLSI

Cited by 270 publications

References 44 publications

Electrical contacts to two-dimensional semiconductors

Electrical contacts to two-dimensional semiconductors

Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

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