2013
DOI: 10.1080/21681724.2013.817021
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3.1–10.6 GHz UWB low-power CMOS power amplifier

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Cited by 5 publications
(9 citation statements)
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“…In this configuration, a common source stage amplifier is followed by a common gate stage to form the cascode topology [23]- [27], [34], [35], [38], [40], [49], [53] as shown in Figure 3. Mostly the cascode power amplifier topology is employed to enhance the performance of the power amplifier.…”
Section: Cascode Power Amplifier Topologymentioning
confidence: 99%
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“…In this configuration, a common source stage amplifier is followed by a common gate stage to form the cascode topology [23]- [27], [34], [35], [38], [40], [49], [53] as shown in Figure 3. Mostly the cascode power amplifier topology is employed to enhance the performance of the power amplifier.…”
Section: Cascode Power Amplifier Topologymentioning
confidence: 99%
“…Mostly the cascode power amplifier topology is employed to enhance the performance of the power amplifier. There are several advantages of this configuration including high bandwidth, boost gain, less slew rate, high stability and reducing miller capacitances [23]- [27], [34], [35], [38], [40], [49], [53]. Also, better isolation between the input and output ports is attained by the cascode scheme.…”
Section: Cascode Power Amplifier Topologymentioning
confidence: 99%
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“…All the Si CMOS power amplifiers proposed in [25] and [26] are operating in more than 100 GHz, which predicts that on chip transceivers could be widely used in near future. In [27], a Si CMOS power amplifier with 21 mW power consumption is introduced. Comparing with other processes power amplifier, Si CMOS power amplifier has the lowest power consumption, highest integration level, and lowest fabrication cost.…”
Section: A Full Cmos Power Amplifiermentioning
confidence: 99%