3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion

Hershberg, Benjamin; Dermit, Davide; Liempd, Barend van; Martens, Ewout; Markulic, Nereo; Lagos, Jorge; Craninckx, Jan

doi:10.1109/isscc.2019.8662290

Cited by 26 publications

(7 citation statements)

References 5 publications

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“…The pipelined concept in analog-to-digital converter can be traced back to the 1960s when Servin from Texas Instruments presented a 1 b/stage pipelined ADC in a patent [162] , as captured in Fig. 17.…”

Section: Pipeline Hybrid Adcsmentioning

confidence: 99%

Trending IC design directions in 2022

Chan¹,

Cheng²,

Deng³

et al. 2022

J. Semicond.

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For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

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Section: Pipeline Hybrid Adcsmentioning

confidence: 99%

Trending IC design directions in 2022

Chan¹,

Cheng²,

Deng³

et al. 2022

J. Semicond.

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show abstract

“…6 shows the simplified single-ended schematic of the proposed input buffer. It employs a complementary push-pull structure [25] to achieve low power consumption, which almost doubles the trans-conductance. The input signal V in drives the input devices (M 2 , M 3 ) by the level shift capacitors.…”

Section: Fig the Parasitic Capacitor Of Nmosmentioning

confidence: 99%

A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS

Chen¹,

Wu²,

Shen³

et al. 2021

IEICE Electron. Express

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This paper presents a 14bit 500MS/s SHA-less pipelined analog-to-digital converter (ADC) implemented in 40nm CMOS. A highlinearity pseudo-differential push-pull input buffer with an anti-oscillation technique and a nonlinear parasitism eliminate technique is proposed to stably drive the pipelined stages while keeping low distortion. Moreover, a digital controlled aperture-error calibration is also employed with offset of comparators compensated in advance. Measurement results show that the ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) of 66.29dB and a spurious-free-dynamic-range (SFDR) of 85.62dBc at 80.1MHz input.

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“…More importantly, ringamps are more suitable for fine CMOS processes and have application scenarios in various types of ADCs due to the versatility of their structures. In the last decade, many ringamp-based ADC works [24,[29][30][31][32][33][34][35][36][37][38][39] have appeared. Essentially, there are two different directions of the application, one for high resolution (signal-to-noise-and-distortion-ratio (SNDR) ≥ 70 dB) and the other for high speed (sampling rate fs ≥ 500 MHz), such as the dual-deadzone RAMP-based two-step SAR ADC [34], which achieves the highest SNDR for a ringampbased high-resolution ADC, while [33] used a dead zone degeneration technique to realize the fastest sampling rate (fs = 1 GHz) for single-channel implementation.…”

Section: Ring Amplifier Reviewmentioning

confidence: 99%

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

et al. 2021

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A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

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3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion

Cited by 26 publications

References 5 publications

Trending IC design directions in 2022

Trending IC design directions in 2022

A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

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