An mm‐wave distributed amplifier (DA) with high gain‐bandwidth (GBW) product and small chip area is implemented in a 65‐nm CMOS process. The DA consists of five cascode unit cells for high gain and isolation. To achieve a wide bandwidth, a series‐peaking line and an m‐derived section are inserted at the interstage and output networks, respectively, of each cascode unit cell. The transistor size is optimized for compromising the tradeoff between gain and bandwidth. For compact layout, all matching sections and lines are implemented using the microstrip structure. The DA exhibits a measured gain of 8.2 dB and a 3‐dB bandwidth of 65 GHz, thus reaching a GBW of 163 GHz. The return loss at the input and output are both more than 13 dB over the entire bandwidth. Due to compact layout, the chip occupies only 0.5 mm2. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:814–817, 2015