3-D effect of cell designs on the breakdown voltage of power SOI-LDMOS

Suzuki, Yasoji; Kishida, T.; Takano, Hiromu; Shirai, Yasuhiro; Suzumura, M.

doi:10.1109/soi.1996.552530

Cited by 8 publications

(2 citation statements)

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“…Recent publications have shown that lateral SOI power devices can achieve high breakdown voltage by optimizing the two dimensional (2D) device parameters in accordance with the RESURF principle[l] [2].The development of new high voltage LDMOS power technologies and novel power device structures has traditionally been guided by an experimental approach. With the advent of increasingly complex racetrack and interdigitated power device layout of high power and high voltage devices, the traditional empirical approach has become expensive and time consuming.…”

Section: Introductionmentioning

confidence: 99%

Combining 2D and 3D Device Simulations for Optimizing LDMOS Design

Lin¹,

Sheu

Yang

et al. 2010

ECS Trans.

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Lateral DMOS power devices can achieve high breakdown voltage by optimizing the two dimensional (2D) device parameters in accordance with the RESURF principle. However, in practice, it is also necessary to optimize the three dimensional (3D) device parameters in order to support a given breakdown voltage. In this paper, We report the effect of 3D parameters such as the curvatures of the drain and source regions, doping density of LDMOS device with SOI ( Silicon-On-Insulator) substrates based on numerical simulations and analytical solutions using cylindrical coordinates with device simulator "MEDICI" and Synopsys 3D simulator Sentaurus 2009.06-SP2 version. We stress the necessary 3D simulation for power device with racetrack, interdigitated layouts etc.

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Section: Introductionmentioning

confidence: 99%

Combining 2D and 3D Device Simulations for Optimizing LDMOS Design

Lin¹,

Sheu

Yang

et al. 2010

ECS Trans.

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“…However, these models are incapable of describing the three dimensional effect of the circular layout such as electric field crowding due to the curvature of the drain region. In practice, taking 3-D effects into account is important to optimize the device parameters and improve the operating performance [9] .…”

Section: Introductionmentioning

confidence: 99%

A three-dimensional breakdown model of SOI lateral power transistors with a circular layout

2009

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This paper presents an analytical three-dimensional breakdown model of SOI lateral power devices with a circular layout. The Poisson equation is solved in cylindrical coordinates to obtain the radial surface potential and electric field distributions for both fully- and partially-depleted drift regions. The breakdown voltages for N+N and P+N junctions are derived and employed to investigate the impact of cathode region curvature. A modified RESURF criterion is proposed to provide a design guideline for optimizing the breakdown voltage and doping concentration in the drift region in three dimensional space. The analytical results agree well with MEDICI simulation results and experimental data from earlier publications.

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Modeling Kirk effect of RESURF LDMOS

Sun

Shi

2005

Solid-State Electronics

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3-D effect of cell designs on the breakdown voltage of power SOI-LDMOS

Cited by 8 publications

References 0 publications

Combining 2D and 3D Device Simulations for Optimizing LDMOS Design

Combining 2D and 3D Device Simulations for Optimizing LDMOS Design

A three-dimensional breakdown model of SOI lateral power transistors with a circular layout

Modeling Kirk effect of RESURF LDMOS

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