3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications

Adam, Gina C.; Hoskins, Brian D.; Prezioso, M.; Merrikh-Bayat, Farshad; Chakrabarti, Bhaswar; Strukov, Dmitri B.

doi:10.1109/ted.2016.2630925

Cited by 191 publications

(127 citation statements)

References 35 publications

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“…[33] Pt group metals are also studied as future sub-7 nm interconnect metal lines as they show comparable or even lower resistivity than Cu at such dimension due to a weaker thickness dependence of the resistivity. [16,32] On the other hand, we observed that when sweeping to a sufficiently high negative voltage (about −2 V), the current drops dramatically to the pristine level or lower (process 3). By precisely measuring the width of TE and BE with scanning electron microscope (SEM), including consideration of BE side wall effect (as shown in Figure 1c), we obtained effective memristor sizes of 25, 50, 100, and 400 nm, respectively (see Supporting Information).…”

Section: Memristor and Cmos Integrationmentioning

confidence: 79%

“…[6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. Recently, many reports demonstrated enouraging results using multiple-bits in HfO x , TaO x , and other oxide memristors for neuromorphic computing applications, [23][24][25]31,32] making these highly promising if CMOS-integrated nanoscale devices can be demonstrated wtih wide dynamic range and promising yield numbers.Using memristors, such as oxide and phase change resistive switches, as tunable resistors to construct analog computing hardware accelerators is gaining keen attention. [4] However, existing demonstrations have a narrow dynamic range and achieving multiple low conductance levels is challenging.…”

mentioning

confidence: 99%

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Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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in computing accelerators compared to high density storage-class memory, it is frequently important in computing applications to program multiple bits of information within every device by achieving many distinct conductance levels, while keeping the operating currents lower especially at the high conductance states. Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy. For example, in analog matrix-vector multiplication, voltage drops across metal interconnect lines cause computational errors and, therefore, the memristor array size must be limited. [6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. This further benefits the energy and area efficiency by amortizing the costs of anolog to digital converters (ADC) required in the circuit. [4] However, existing demonstrations have a narrow dynamic range and achieving multiple low conductance levels is challenging. A larger ratio between the high and low conductances (on/off ratio) helps in achieving more distinct programmable low conductance levels. In addition, memristors are required to be integrated with CMOS circuits in many such applications. For instance, a 1-transistor-1-memristor (1T1M) combination provides in situ current compliance through gate voltage modulation so that the memristor can be programmed in an analog manner. [12,16,25] This brings another challenge: compatibility of memristor and CMOS. This includes not only material and fabrication compatibility, but also CMOS performance meeting the memristor operating requirements as both continue size scaling. Thus, it is essential to demonstrate all the aforementioned properties in nanometer-scale memristors repeatedly and reproducibly.Among various forms of memristors, oxide memristors outperform others by possessing the advantages of lower programming and computing energy, favorable scaling in cell size, [10,11,30] and CMOS-compatibility in materials and fabrication. Recently, many reports demonstrated enouraging results using multiple-bits in HfO x , TaO x , and other oxide memristors for neuromorphic computing applications, [23][24][25]31,32] making these highly promising if CMOS-integrated nanoscale devices can be demonstrated wtih wide dynamic range and promising yield numbers.Using memristors, such as oxide and phase change resistive switches, as tunable resistors to construct analog computing hardware accelerators is gaining keen attention. Such accelerators have demonstrated the potential to significantly outperform digital computers in highly relevant applications such as machine learning and image processing. However, improvements in device-level performance of memristors, including reducing power consumption and high current-induced metal migration in interconnects, need continued developments. Nanoscaling and complementary metal-oxide semiconductor (CMOS) integration are also of significant ...

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Section: Memristor and Cmos Integrationmentioning

confidence: 79%

mentioning

confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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show abstract

“…b) Measured change of synaptic connections as a function of the relative timing of pre-and postsynaptic spikes using Al 2 O 3 /TiO 2x , second-order, PCMO, and tunnel junction memristors. [77][78][79] www.advancedsciencenews.com www.advintellsyst.com computing encodes the input data into query vectors and compares them with a set of hypervectors trained from various classes. c) Training scheme of HD computing using RRAM associate memory.…”

Section: Rram-based Designs In Trainingmentioning

confidence: 99%

“…[22,67] Furthermore, 3D stacking techniques can expand the array layers vertically with a minimal impact on the die area. For example, Adam et al demonstrated a two-layer stack RRAM array, [78] where the TiO 2 À x RRAM is fabricated on Si wafer coated with SiO 2 . For example, Adam et al demonstrated a two-layer stack RRAM array, [78] where the TiO 2 À x RRAM is fabricated on Si wafer coated with SiO 2 .…”

Section: D Stacking For Scalabilitymentioning

confidence: 99%

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Yan

Qiao

et al. 2019

Advanced Intelligent Systems

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In‐memory computing is a computing scheme that integrates data storage and arithmetic computation functions. Resistive random access memory (RRAM) arrays with innovative peripheral circuitry provide the capability of performing vector‐matrix multiplication beyond the basic Boolean logic. With such a memory–computation duality, RRAM‐based in‐memory computing enables an efficient hardware solution for matrix‐multiplication‐dependent neural networks and related applications. Herein, the recent development of RRAM nanoscale devices and the parallel progress on circuit and microarchitecture layers are discussed. Well suited for analog synapse and neuron implementation, RRAM device properties and characteristics are emphasized herein. 3D‐stackable RRAM and on‐chip training are introduced in large‐scale integration. The circuit design and system organization of RRAM‐based in‐memory computing are essential to breaking the von Neumann bottleneck. These outcomes illuminate the way for the large‐scale implementation of ultra‐low‐power and dense neural network accelerators.

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“…This indicates highly dense 3D structures with a very large number of memristors within very close proximity of one another will be the norm, and coupling memristor theory is of fundamental significance to this field. The use of memristive crossbar architectures has been gaining much traction in computing large sets of data [11][12][13][14], and the theory behind memristive coupling is absolutely essential in ensuring information is not lost due to undesirable coupling, or by manufacturing more efficient modes of information storage by utilizing coupling theory.…”

Section: Introductionmentioning

confidence: 99%

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

Eshraghian¹,

Iu²,

KamranEshraghian³

2018

Memristor and Memristive Neural Networks

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This chapter explores the dynamic behavior of dual flux coupled memristor circuits in order to explore the uncharted territory of the fundamental theory of memristor circuits. Neuromorphic computing anticipates highly dense systems of memristive networks, and with nanoscale devices within such close proximity to one another, it is anticipated that flux and charge coupling between adjacent memristors will have a bearing upon their operation. Using the constitutive relations of memristors, various cases of flux coupling are mathematically modeled. This involves analyzing two memristors connected in composite, both serially and in parallel in various polarity configurations. The new behavior of two coupled memristors is characterized based on memristive state equations, and memductance variation represented in terms of voltage, current, charge and flux. The rigorous mathematical analysis based on the fundamental circuit equations of ideal memristors affirms the memristor closure theorem, where coupled memristor circuits behave as different types of memristors with higher complexity.

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3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications

Cited by 191 publications

References 35 publications

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Modeling of Coupled Memristive-Based Architectures Applicable to Neural Network Models

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