30-100-MHz NPN-only variable-gain class-AB instantaneous companding filters for 1.2-V applications

El-Gamal, M.N.; Baki, R.A.; Bar-Dor, A.

doi:10.1109/4.890298

Cited by 26 publications

(20 citation statements)

References 17 publications

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“…This V/I converter is a modified version of the CMOS I/I converter discussed in [15]. Analysis of the feedback loop composed of Q 1 -Q 5 shows that [6]. Transistor Q 8 carries the same current as Q 2 .…”

Section: The Input and Output Interface Circuitrymentioning

confidence: 99%

A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding

Baki

El-Gamal

2001

Proceedings of the 2001 International Symposium on Low Power Electronics and Design - ISLPED '01

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A seventh-order 0.05 o equiripple linear-phase continuous-time filter employing, for the first time, instantaneous companding, was designed and integrated in a mature bipolar process. The amount of boost (up to 13dB) and group-delay adjustment (30%) are digitally programmable. The DC gain is controllable up to 10dB, and the -3dB frequency (f c ) is tunable from 5 to 70MHz. The output swing for 1% THD is higher than 100mV pp , with a 1.5V supply. The filter consumes very low power (5-13mW for f c = 70MHz) compared to conventional implementations (e.g. 120mW for f c = 100MHz [1]). INTRODUCTIONThe continuous decrease of the supply voltages of modern integrated circuit technologies often necessitates an increase in the power consumption of conventional analog circuit processors, in order to maintain the same Dynamic Range (DR) and chip area for a given bandwidth [2]. To mitigate this restriction, the use of companding-based signal processors was proposed [3]- [4]. The last ten years have seen a growing interest in employing companding for continuous-time filtering. This was paralleled by the design and fabrication of several integrated log-domain filter circuits in a variety of technologies (e.g.[5]- [11]). These implementations were mostly low-order filters for proof of concept and / or performance exploration; they did not target particular applications or specifications. In order to gain industrial acceptance, the performance of companding-based filters needs to match, if not exceed, the performance of conventional filtering schemes, and should be evaluated in the context of concrete applications. Recently, a micropower log-domain filter for the Digital European Cordless Telephone (DECT) standard was reported [10]. Hard-disk-drive (HDD) read channels is another application where the requirements on filtering is constantly on the rise in terms of power consumption, tunability, speed, and robustness [12]. The objective of the work presented in this paper is to design a companding-based prefilter for HDD applications which exceeds state-of-the-art bipolar/BiCMOS designs in terms of voltage supply and power consumption (5mW without boost and equalization for f c = 70MHz versus 120mW for f c = 100MHz in [1]), while satisfying the requirements of partial response maximum likelihood (PRML) read channel front-ends. In servo mode, the filter has a cutoff frequency as low as 5MHz and dissipates less than 500µW. Figure 1 shows the overall structure of the 7 th -order filter presented in this paper, along with a summary of the system specifications (details in Section 5). The input signal is compressed before being processed, which ensures signal integrity over a large range of signal levels. At the output, the signal is expanded to restore its DR. When the compression / uncompression are logarithmic / exponential, the resulting filter is known as a "log-domain filter" [13]. CONCEPT OF LOG-DOMAIN FILTERINGThe concept of log-domain filtering is illustrated in Fig. 2 (a) for a simple first-order filter. The input signal v IN ,...

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Section: The Input and Output Interface Circuitrymentioning

confidence: 99%

A low-power, 5-70MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding

Baki

El-Gamal

2001

Proceedings of the 2001 International Symposium on Low Power Electronics and Design - ISLPED '01

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“…While the relative performance of these CMOS filters is encouraging, it is important to point out that further implementations which make use of the bipolar integrator in [8] have been fabricated in more advanced bipolar processes, and operating frequencies from 30 -100 MHz have been reported [11]. Such filter eut-off frequencies are likely beyond the range which can be achieved in CMOS technology using lateral PNP devices.…”

Section: -A Comparison Of Filter Performancementioning

confidence: 99%

“…The filter will therefore conform to the block diagram presented in Figure 1.2 in Chapter 1, in which only single compression and expansion stages are present. A compact all-CMOS implementation of a VII converter, adapted from [11], is shown in Figure 3.7. In this circuit, transistors Ml and M z are each biased with a constant current I vi ' while the diode connection between the gate of M z and the drain of M Za provide a reference voltage to the gate of Ml' This arrangement ensures that the source of Ml will be biased to DC ground.…”

Section: -Input Compression 1output Expansion and Interface Circuitrymentioning

confidence: 99%

“…al. [11] in the design of a high-frequency third-order filter, shown to be capable of operation at up to 100 MHz while operating from a 1.2 V supply.…”

Section: -_mentioning

confidence: 99%

“…The cell has been adapted from a low voltage NPN-only integrator described in [1], [11]. The circuit below has two inputs, labelled as Vp and Vn, and an output labelled as V out 1.…”

Section: -The Log-domain Integratormentioning

confidence: 99%

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