30.3 A 512Gb 3b/Cell 7<sup>th</sup> -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface

Cho, Ji-Ho; Kang, Dong‐Ku; Park, Jongyeol; Nam, Sang-Wan; Song, Jungho; Jung, Bongjin; Lyu, Jaedoeg; Lee, Hogil; Kim, Won‐Tae; Jeon, Hongsoo; Kim, Sung Hoon; Kim, In-Mo; Son, Jooyoung; Kang, Kyoungtae; Shim, Sang-Won; Park, JongChul; Lee, Eungsuk; Kang, Kyung-Min; Park, Sang-Won; Lee, Jaeyun; Moon, Seung Hyun; Kwak, Pansuk; Jeong, Byunghoon; Lee, Cheon An; Kim, Ki-Sung; Ko, JaeYoun; Kwon, Taehong; Lee, Jun-Ha; Lee, Yohan; Kim, Chaehoon; Lee, Myeong-Woo; Yun, Jeong-Yun; Lee, HoJun; Choi, Yong‐Sang; Hong, Sungchul; Park, Jonghoon; Shin, Yoonsung; Kim, Hojoon; Kim, Hansol; Yoon, Chi-Weon; Byeon, Dae Seok; Lee, Seungjae; Lee, Jin-Yub; Song, Jaihyuk

doi:10.1109/isscc42613.2021.9366054

Cited by 22 publications

(7 citation statements)

References 5 publications

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“…From the evaluation results in Figure 14a,b, we know that the effect of 200 erase cycles on RBER can be neglected even at the end-of-life (EOL) stage. Although there is an RBER difference of 1∼2 bits, it results from an avoidable noise effect such as RTN (Random Telegraph Noise) [35], not a reliability difference. However, when we apply the pre-condition P/E cycles as a source of electrical stress, we should consider how much…”

Section: Side Effects Analysismentioning

confidence: 99%

Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Kim,

Seo,

Kim

2024

Eng

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In order to successfully achieve mass production in NAND flash memory, a novel test procedure has been proposed to electrically detect and screen the channel hole defects, such as Not-Open, Bowing, and Bending, which are unique in high-density 3D NAND flash memory. Since channel hole defects lead to catastrophic failure (i.e., malfunction of basic NAND operations), detecting and screening defects in advance is one of the key challenges of guaranteeing the quality of flash products in the NAND manufacturing process. Based on analysis of the physical and electrical mechanisms of the channel hole defect, we have developed a two-step test procedure that consists of pattern-based and stress-based screen methodologies. By optimizing test patterns depending on the type of defect, the pattern-based screen is effective for detecting the type of Hard channel hole defects. The stress-based screen is carefully implemented to detect hidden Soft channel hole defects without degrading the reliability of NAND flash memory. In addition, we have attempted to further optimize the current version of our technique to minimize test time overhead, thus enabling 72.2% improvement in total test time. Experimental results using real 160 3D NAND flash chips show that our technique can efficiently detect and screen out various types of channel hole defects with minimum test time and negligible degradation in the flash reliability.

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Section: Side Effects Analysismentioning

confidence: 99%

Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Kim,

Seo,

Kim

2024

Eng

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“…The 3D NAND flash was developed more than ten years ago in 2007 [ 10 ], and the first TLC 3D BiCS flash memory with 32 stacked layers was demonstrated by Toshiba in 2015 [ 11 ]. Currently, 174 staking storage layers [ 1 , 2 ] as well as HLC operation mode [ 4 ] have been realized and demonstrated. So far, 3D NAND flash has been utilized in many kinds of storage products, especially in smartphones, personal computers, and data centers.…”

Section: Background and Related Workmentioning

confidence: 99%

“…For charge-trap (CT) 3D NAND flash memory, the endurance can largely be improved because the effects of the tunneling layer degradations are weak, and the program time can be faster because the effects of inter-cell interference (ICI) are well suppressed with larger cell-to-cell space. Recently, a 3D NAND with more than 170 layers was announced by the NAND flash makers [ 1 , 2 ]; more impressively, quadruple-level-cell (QLC, 4 bits/cell), penta-level-cell (PLC, 5 bits/cell), and even hexa-level-cell (HLC, 6 bits/cell) operation modes have been demonstrated [ 3 , 4 ]. All these fundamental developments as well as design-technology co-optimizations (DTCO) will drive 3D NAND flash to the mainstream non-volatile memories in the near future [ 5 ].…”

Section: Introductionmentioning

confidence: 99%

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Chen

Lin

et al. 2021

Micromachines

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Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

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“…TCAT subsequently evolved into V-NAND architecture, which has 32-stacked word line (WL) layers [26][27][28]. The industry has moved beyond 12x-stacked WL layers and achieved a 17x-stacked V-NAND [29,30]. As the memory industry transitions from planar to 3D scaling, traditional device reliability issues must still be considered.…”

Section: Introductionmentioning

confidence: 99%

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

Chiu

Shirota

2021

Electronics

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NAND Flash memories have gained tremendous attention owing to the increasing demand for storage capacity. This implies that NAND cells need to scale continuously to maintain the pace of technological evolution. Even though NAND Flash memory technology has evolved from a traditional 2D concept toward a 3D structure, the traditional reliability problems related to the tunnel oxide continue to persist. In this paper, we review several recent techniques for separating the effects of the oxide charge and tunneling current flow on the endurance characteristics, particularly the transconductance reduction (ΔGm,max) statistics. A detailed analysis allows us to obtain a model based on physical measurements that captures the main features of various endurance testing procedures. The investigated phenomena and results could be useful for the development of both conventional and emerging NAND Flash memories.

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30.3 A 512Gb 3b/Cell 7^th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface

Cited by 22 publications

References 5 publications

Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

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30.3 A 512Gb 3b/Cell 7th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface

Cited by 22 publications

References 5 publications

Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Technique for Profiling the Cycling-Induced Oxide Trapped Charge in NAND Flash Memories

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Product

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30.3 A 512Gb 3b/Cell 7^th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface