30.9 Normally-off computing with crystalline InGaZnO-based FPGA

Aoki, Takuya; Okamoto, Yuki; Nakagawa, Takashi; Ikeda, Masataka; Kozuma, Munehiro; Osada, Takeshi; Kurokawa, Yasuyoshi; Ishihara, Takayuki; Yamade, Naoto; Okazaki, Yutaka; Miyairi, Hiroo; Fujita, Masahiro; Koyama, Jun; Yamazaki, Shunpei

doi:10.1109/isscc.2014.6757531

Cited by 26 publications

(19 citation statements)

References 3 publications

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“…In the previous CAAC-IGZO FPGA, it was intended that a V th drop in the PRS be resolved by boosting PRS cfg with capacitive coupling between an input signal line and the floating gate N cfg [29]. However, the boosting effect is insufficient when the amplitude of the input signal decreases in subthreshold operation; therefore, further mechanisms are necessary.…”

Section: Low-voltage Design Of Caac-igzo Fpga a Design Issuesmentioning

confidence: 99%

“…For example, displays [12]- [15], large scale integrations such as memories [16]- [20], CPUs [21]- [26], and FPGAs [1], [2], [27]- [31], and image sensors [32]- [36] have been reported to exhibit a variety of features that can be achieved with CAAC-IGZO FETs, e.g., low power consumption and additional functions owing to the ultralow leakage. A multicontext (MC) FPGA that includes nonvolatile configuration memory with a CAAC-IGZO FET (CAAC-IGZO FPGA) [1], [2], [27]- [31] features the following characteristics: 1) fine-grained power gating (PG) [27] capable of controlling power supply to individual PLEs; 2) MC architecture [28] capable of fast configuration switching; 3) data load/store between a volatile register and its dedicated nonvolatile shadow register before and after power shutoff by fine-grained PG [29]; 4) normally OFF driving [29] to support these functions.…”

Section: Introductionmentioning

confidence: 99%

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Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch

Kozuma

Okamoto

Nakagawa

et al. 2017

IEEE Trans. VLSI Syst.

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A field-programmable gate array (FPGA) using a crystalline oxide semiconductor of c-axis-aligned crystal indium-gallium-zinc oxide (CAAC-IGZO) has been developed, which is capable of subthreshold operation used for energy harvesting. To achieve subthreshold operation, the CAAC-IGZO FPGA has a structure designed as an extension of a boosting pass gate using a CAAC-IGZO FET and employs overdriving of a programmable routing switch and a programmable power switch for power gating (PG). A CAAC-IGZO FET is used to give an ideal floating gate with excellent charge retention. A chip fabricated using a 0.8-µm CAAC-IGZO/ 0.18-µm CMOS hybrid process achieves subthreshold operation while maintaining the features required for normally off computing proposed in our previous study. Specifically, these features are realized by fine-grained PG for individual programmable logic elements (PLEs), fast configuration switching between contexts, and load/store between a volatile register and a nonvolatile shadow register in the PLEs. The chip operation at a minimum operating voltage of 180 mV with a combinational circuit configuration is demonstrated. With a sequential circuit configuration, the chip operates at a minimum operating voltage of 190 mV with 12.5 kHz, and the minimum power-delay product is 3.40 pJ/operation at 330 mV.Index Terms-c-axis-aligned crystal indium-gallium-zinc oxide (CAAC-IGZO), crystalline oxide semiconductor, fieldprogrammable gate array (FPGA), low voltage, multicontext (MC), nonvolatile memory, nonvolatile shadow register, normally OFF computing, power gating (PG), subthreshold operation.

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Section: Low-voltage Design Of Caac-igzo Fpga a Design Issuesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch

Kozuma

Okamoto

Nakagawa

et al. 2017

IEEE Trans. VLSI Syst.

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“…The main concept is to isolate the nonvolatile device from the CMOS flip-flop with switches (M1 and M2), and the nonvolatile devices perform store/recall operations only when power failures happen. [3,4,5,6,7,8]. Table 1 compares their performance of data store and recall.…”

Section: Nonvolatile Flip-flopmentioning

confidence: 99%

Ambient energy harvesting nonvolatile processors

Liu

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

127

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Energy harvesting is gaining more and more attentions due to its characteristics of ultra-long operation time without maintenance. However, frequent unpredictable power failures from energy harvesters bring performance and reliability challenges to traditional processors. Nonvolatile processors are promising to solve such a problem due to their advantage of zero leakage and efficient backup and restore operations. To optimize the nonvolatile processor design, this paper proposes new metrics of nonvolatile processors to consider energy harvesting factors for the first time. Furthermore, we explore the nonvolatile processor design from circuit to system level. A prototype of energy harvesting nonvolatile processor is set up and experimental results show that the proposed performance metric meets the measured results by less than 6.27% average errors. Finally, the energy consumption of nonvolatile processor is analyzed under different benchmarks.

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“…MC-FPGAs [30]- [35] using nonvolatile memory cells including CAAC-IGZO FETs as CM have been developed. These MC-FPGAs do not require reconfiguration when resuming computation after PG because they include nonvolatile CMs, and have high operating speed owing to the boosting effect of pass gates included in routing switches [30]- [35].…”

Section: Introductionmentioning

confidence: 99%

“…These MC-FPGAs do not require reconfiguration when resuming computation after PG because they include nonvolatile CMs, and have high operating speed owing to the boosting effect of pass gates included in routing switches [30]- [35]. Since low-power CM for data retention is realized with a small number of elements, FPGAs can easily employ a fine-grained MC architecture and are capable of performing fine-grained PG [33], [34].…”

Section: Introductionmentioning

confidence: 99%

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Aoki

Okamoto

Nakagawa

et al. 2015

IEEE J. Solid-State Circuits

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Normally-off computing (Noff computing) using a multicontext field programmable gate array (MC-FPGA) consisting of crystalline oxide semiconductor FETs has been developed. The Noff computing discussed in this paper is a control architecture for an MC-FPGA capable of performing fine-grained power gating on each programmable logic element (PLE) whose registers include a volatile register and also a nonvolatile shadow register for storing and loading data in the volatile register. The MC-FPGA performs fine-grained control of power supplied only to PLEs contributing to effective calculation, when context switching happens. With an MC-FPGA fabricated with a hybrid process of a 1.0 µm crystalline oxide semiconductor FET on a 0.5 µm CMOS FET, it has been confirmed that the proposed Noff computing can resume the previous task when a context switches back to it, increases PLE use efficiency, and reduces the power consumption by 27.7% at operating frequencies of 20 MHz with a driving voltage of 2.5 V.Index Terms-CAAC-IGZO, crystalline IGZO, crystalline oxide semiconductor, field programmable gate array, multicontext, nonvolatile memory, normally-off computing, oxide semiconductor, power gating, shadow register. 0018-9200

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30.9 Normally-off computing with crystalline InGaZnO-based FPGA

Cited by 26 publications

References 3 publications

Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch

Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch

Ambient energy harvesting nonvolatile processors

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

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