31.1 An 82mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% Efficiency

Matamura, Atsushi; Nishimura, Naoaki; Birdsong, Preston; Bandyopadhyay, Abhishek; Spirer, Adam; Markova, Mariana; Liu, Shaolong

doi:10.1109/isscc42613.2021.9365773

Cited by 3 publications

(4 citation statements)

References 5 publications

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“…Ideally, no input-related content should be present in D 2 such that the gain mismatch of the two DAC segments contributes only shaped noise. In [2,5], a 1 st -order DSM is used, which could produce idle tones at small signal levels, leading to harmonic content in D 2 . The gain mismatch between the segments will then allow some of this content to leak into the output.…”

Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

“…Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak THD+N of about −98dB [2,3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, ISI, and intermodulation distortion.…”

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confidence: 99%

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3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Zhang

Berkhout²,

Makinwa

et al. 2023

2023 IEEE International Solid- State Circuits Conference (ISSCC)

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Class-D amplifiers (CDAs) are widely used in audio applications where a high power efficiency is required. As most audio sources are digital nowadays, implementing digitalinput CDAs results in higher levels of integration and lower cost. However, prior open-loop digital-input CDAs suffer from high jitter sensitivity and output-stage distortion. In [1], jitter sensitivity at small signal levels is mitigated using a buck-boost converter that adaptively lowers the supply at the expense of extra external components and reduced power efficiency. Prior closed-loop digital-input CDAs employing multi-bit current-steering [2] or resistive [3] DACs are less sensitive to jitter, but their DR is limited to about 115dB. DAC non-idealities and intermodulation distortion are also challenges, and prior works only achieved a peak THD+N of about −98dB [2,3]. This paper presents a digital-input CDA that achieves high DR by combining a low-noise capacitive DAC (CDAC) with dedicated techniques to mitigate DAC mismatch, ISI, and intermodulation distortion. A prototype implemented in a 0.18μm BCD process achieves 120.9dB DR and −111.2dB peak THD+N. Furthermore, it can deliver 13W/23W at 10% THD into an 8Ω/4Ω load with a 90%/86% efficiency.

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Section: Green Open Access Added To Tu Delft Institutional Repositorymentioning

confidence: 99%

mentioning

confidence: 99%

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Zhang

Berkhout²,

Makinwa

et al. 2023

2023 IEEE International Solid- State Circuits Conference (ISSCC)

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“…Many ways to apply feedback to digital class-D amplifier have been published in literature [5,6,13,[21][22][23][24][25][26][27][28][29][30]. Hybrid types of amplifiers that generated PWM digitally have been presented where the output stage has an analog loop to mitigate supply variations [5,13].…”

Section: Feedbackmentioning

confidence: 99%

“…In [29], one ADC is used to digitize both the input and the feedback signal after summation. The amplifier in [30] has a signal level dependent mode control scheme that can change the modulation and pulse patterns to save power.…”

Section: Feedbackmentioning

confidence: 99%

Active PWM ripple reduction in class-d amplifiers using digital loop filters

Lokin¹

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The research field around sound reproduction is driven by a desire to continuously pack more powerful amplifiers in a small fan-less enclosure while providing state-of-the-art noise and distortion performance. Class-D amplifiers are a perfect candidate for these requirements, specifically because of the inherently low dissipation in their switching power stage with respect to more conventional linear amplifiers. There is, however, always a caveat: switching high currents at high frequencies causes electromagnetic emissions that could interfere with the correct operation of other electronic devices. Regulations limit the amount of electromagnetic interference (EMI) that devices are allowed to emit to maintain interoperability between the many electronic devices in the Internet of things (IoT) era.Speakers are commonly connected to an amplifier using leads of several meters. These leads double as an antenna for high frequency signals above the audio band, such as the switching frequency and its harmonics or parasitic ringing in the output stage, thereby causing unwanted radiated emissions. This thesis is focused on reducing the EMI due to the residual power after the output filter at the pulse-width modulation (PWM) frequency, the so called ripple. Examples in literature reduce the power at the PWM frequency and its harmonics by applying spread spectrum modulation to smear power out over a larger bandwidth. However, in this way they still radiate the same amount of power, just not concentrated at distinct frequencies. To reduce the ripple current through the speaker leads, it is possible to use a higher order filter, use a multi-phase or multi-level output stage or to inject a cancellation signal after the output filter. In the research field of power electronics, cancellation schemes have been presented. First the disturbance is sensed and processed and afterwards a cancellation signal is synthesized and injected into the circuit. The processing can be done using a feedback or feed-forward topology, each having its advantages and disadvantages.An extensive case study on multi-phase systems is done to evaluate their merits in reducing the ripple current after the output filter. In a multiphase system, multiple half-bridges are combined in a parallel fashion to drive one or both sides of the load. Interleaving of the PWM carriers in the modulator corresponding to each half-bridge provides a reduction in the observed ripple current after combining the half bridge outputs in the output filter. The effect of adding more phases on the amount of ripple is vii ix ABSTRACT high-frequency poles.In summary, this thesis has shown a technique to reduce the ripple current after the output filter. Thereby the amount of EMI that can be radiated off the speaker leads decreases. The effect of unit delays in the loop has been mitigated by applying a special filter design method to obtain a more stable system. A prototype has been made around an existing amplifier to show the effectiveness of the proposed feedback ripple reduction so...

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21.1 A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme

Zhang,

Chen

et al. 2024

2024 IEEE International Solid-State Circuits Conference (ISSCC)

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31.1 An 82mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier with -93dB THD+N, 113dB SNR and 93% Efficiency

Cited by 3 publications

References 5 publications

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

3.1 A 120.9dB DR, -111.2dB THD+N Digital-Input Capacitively-Coupled Chopper Class-D Audio Amplifier

Active PWM ripple reduction in class-d amplifiers using digital loop filters

21.1 A 121.7dB DR and -109.0dB THD+N Filterless Digital-Input Class-D Amplifier with an HV Multibit IDAC Using Tri-level Output and Employing a Transition-Rate-Balanced Bidirectional RTDEM Scheme

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