31.4: A 3.4Gbps/lane Low Overhead Clock Embedded Intra‐panel Interface for High Resolution and Large‐Sized TFT‐LCDs

Oh, Wook; Kim, Jin-Ho; Chang, Young-Hwan; Kim, Tea-Jin; Lee, Jae-Youl; Nah, Kyung-Suc; Hwang, Gyoo-Cheol

doi:10.1002/j.2168-0159.2013.tb06230.x

Cited by 5 publications

(3 citation statements)

References 9 publications

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“…Mostly to make the data transition edges, in the PLL based CDR, use balance code such as 8B/10B or 4B/5B. This codes increase in protocol overhead of as much as 25% [13].For an example, in the CEDS protocol [14], the width of dummy bits is two UI. For the UI of 250ps, this width is not the bottleneck for phase alignment.…”

Section: Topology and Retiming Scheme Of Cdrmentioning

confidence: 99%

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

Zhengcai¹

2019

Symp Digest of Tech Papers

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This work presents a front‐end circuits including of the equalizer and clock/data recovery (CDR) circuits in the source driver ICs (SDICs) for the TFT‐LCD intra‐panel interfaces. For 4K2K LCD TV, the data rate of SDICs has been increased to 5Gbps per lane, so it is a challenge to develop the front‐end circuits when they suffered from the serious ISI and large jitters in received data. In the front‐end circuits meeting the BOE’s CHPI specification, a cascade equalizer are used to widen the eye diagram to reduce BER and a dual loop CDR circuits are used to tolerate the large input jitter and power noise.

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Section: Topology and Retiming Scheme Of Cdrmentioning

confidence: 99%

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

Zhengcai¹

2019

Symp Digest of Tech Papers

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“…Therefore, it can run at higher speed than the corresponding inverter-based ring oscillator, whose maximum achievable frequency is highly correlated with the process technology. For example, as high definition (HD), ultra-high definition (UHD) and 8K (Quard-UHD) TVs are being adopted in the television market, the throughput of the intra-panel interface from the timing controller (TCON) to the source-driver IC (SIC) can exceed 10 Gbps, while the SIC circuit process technology is typically limited to 180 nm CMOS because of high voltages needed for pixel driving [4][5][6][7]. To enable the next generation display interface, CML-based ring oscillators running at higher frequency with conventional process technologies are highly desired.…”

Section: Introductionmentioning

confidence: 99%

The Oscillation Frequency of CML-based Multipath Ring Oscillators

Song

Kim²,

Xiong³

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor α, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor α an attractive option for lower power applications.

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“…Although voltage regulator is adopted to suppress voltage variation of VCO, CDR may be severely affected by ground noise caused by low-voltage digital switching and high voltage output driving operations in the column driver. Clock embedded intra-panel interface with PLL-based CDR is also proposed to achieve 3.4Gbps data rate [2]. Although PLL-based CDR is adopted to minimize protocol overhead, more complex circuitry in PLL-based CDR requires careful effort to design them and CDR may be sensitive to power supply noise due to noisy environment in the column driver.…”

Section: Introductionmentioning

confidence: 99%

P‐176L: Late‐News Poster: A 3.7Gb/s Clock‐embedded Intra‐Panel Interface for the Large‐sized UHD 120Hz LCD TV Application

Jeon

Kim

Cho

et al. 2014

Symp Digest of Tech Papers

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An Intra-panel interface that supports 3.7Gb/s data transmission on the ultra-high definition (UHD) TV application is proposed. The interface channel of display module for UHD TV consists of long PCB traces and flexible flat cable (FFC), which severely degrade the signal quality of transmitted signal. To support over 3Gb/s data rate in the interface channel of UHD display, the receiver in the column driver is equipped with a continuous-time linear equalizer (CTLE) with adjustable equalization step and data sampler with improved setup and hold time. The transmitter for the proposed interface is implemented using a field programmable gate array (FPGA). The column driver with the proposed receiver is fabricated with a 0.18um high-voltage CMOS process. The proposed interface is verified with 84-inch UHD (3840RGBx2160) resolution TFT-LCD module with 10-bit color depth and 120Hz refresh rate for large-sized TV application. The proposed receiver in the column driver achieves 3.7Gb/s data rate in wafer test and 3.1Gbps data rate that is the maximum data rate in the pattern generator at the LCD module with 80-cm FFC.. Author

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31.4: A 3.4Gbps/lane Low Overhead Clock Embedded Intra‐panel Interface for High Resolution and Large‐Sized TFT‐LCDs

Cited by 5 publications

References 9 publications

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

13.2: Equalizer and Clock/Data Recovery Circuits in SDICs for Intra‐Panel Interface

The Oscillation Frequency of CML-based Multipath Ring Oscillators

P‐176L: Late‐News Poster: A 3.7Gb/s Clock‐embedded Intra‐Panel Interface for the Large‐sized UHD 120Hz LCD TV Application

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