This paper presents a GaAs IEEE floating point standard single precision multipliex A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The combination of the fast arithmetic architecture and compact layout svle achieves 4ns multiplication time with 3.5W power dissipation at 75°C giving 14 mW/UHt The area is 2.43" by 3.77" (excluding pads) and uses 28,000 transistors to give a density of 3056 transistordmd for 0.8-pm GaAs technology.
IntroductionHigh-speed and high-precision computation are required for many digital signal processing, computer graphics, model simulation and image processing applications. Floating point computation is most suitable for these applications because it maintains high precision operation over a wide dynamic range. For microcomputer systems, not only high-speed but also small-sized floating point devices are in great demand Usually floating point chips are designed using siliconbased technology [1]-[3]. Advances in fabrication processes have significantly improved the performance of silicon devices [4, 51. However, GaAs has inherent superiority in electron mobility and saturation velocity, high-temperature operation, and radiation hardness. In a research and development environment, GaAs digital circuits have clearly a beuer power-delay performance than silicon circuits [6]. In recent years GaAs ICs have become increasingly attractive due to their high speed. Also, the yield of GaAs ICs has increased dramatically. However, the relatively low layout density compared to CMOS has tended to limit the utilization of GaAs VLSI circuits.In this paper, we describe a fast, compact 32-bit GaAs floating point multiplier using a new design and layout strategy which takes advantage of the superior performance of GaAs and improves the layout density. A modified carry save array is used in conjunction with Booth's algorithm to reduce the partial product addition and interconnection. A special rounding technique called Trailing-1's Predictor is used to speed up the final addition and rounding. The chip supports IEEE standard 754 single precision format and provides overflow/unMow flags. Tbe chip measures 2.43x3.77" and contains 2 8 . m transistors. 'be simulated result of the multiplication time for the chip is 4ns, with 3.5W power dissipation at 75°C.
Chip ArchitectureA block diagram of the floating point multiplier is shown in Figure 1. The chip consists of an exponent block and a mantissa multiplier block. The exponent block evaluates the sign and exponent in floating point multiplication mode, and detects overilow/unMow. MANTISSA BLDCK m modified carry save I I
