32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography

Abstract

In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. 5, 11, 14However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that incorporates integer linear programming (ILP), phase conflict detection (PCD), and node-deletion bipartization (NDB) methods. We evaluate our approach on both real-world and artificially generated testcases in 45nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout. While we have previously reported other facets of our research on DPL pattern decomposition, 6 the present paper differs from that work in the following key respects: (1) instead of detecting conflict cycles and splitting nodes in conflict cycles to achieve graph bipartization, 6 we split all nodes of the conflict graph at all feasible dividing points and then formulate a problem of bipartization by ILP, PCD 8 and NDB 9 methods; and (2) instead of reporting unresolvable conflict cycles, we report the number of deleted conflict edges to more accurately capture the needed design changes in the experimental results.

Area-Efficient Binarized Neural Network Inference Accelerator Based on Time-Multiplexed XNOR Multiplier Using Loadless 4T SRAM

“…Fig. 19 (b), (c) and (d) shows the layout for the Array 0, Array 1-2 and Array 3, respectively in 32nm technology [27]. All the layouts include the synapse array, neuron, input data buffer, row decoder, column decoder and sense amplifier circuits.…”

Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric

“…For physical layout design and evaluation, 1-D Gridded design rules [41] were used to compare the area of GNTRAM cell with Gridded 8T SRAM cell [42] in 16nm technology node. Regular 6T CMOS SRAM scaled to 16nm technology node was also used for benchmarking.…”

Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit

“…PTM interconnect RC models based on scaled interconnect dimensions were used in conjunction with the PTM transistor models for power and performance evaluation of GNTRAM using HSPICE. For physical layout design and area evaluation of GNTRAM, 1-D gridded design rules [Bencher et al 2009] were used as shown in Table II. For benchmarking against CMOS, 16nm Gridded 8T SRAM cell [Greenway et al 2008] was used, since this SRAM design utilizes the same grid-based design used in GNTRAM. Regular 6T CMOS SRAM scaled to 16nm technology node was also used for benchmarking.…”