As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, earlystage estimation of NoC power has become crucially important. ORION [29] was amongst the first NoC power models released, and has since been fairly widely used for early-stage power estimation of NoCs. However, when validated against recent NoC prototypes -the Intel 80-core Teraflops chip and the Intel Scalable Communications Core (SCC) chip -we saw significant deviation that can lead to erroneous NoC design choices. This prompted our development of ORION 2.0, an extensive enhancement of the original ORION models which includes completely new subcomponent power models, area models, as well as improved and updated technology models. Validation against the two Intel chips confirms a substantial improvement in accuracy over the original ORION. A case study with these power models plugged within the COSI-OCC NoC design space exploration tool [23] confirms the need for, and value of, accurate early-stage NoC power estimation. To ensure the longevity of ORION 2.0, we will be releasing it wrapped within a semi-automated flow that automatically updates its models as new technology files become available.

In this work, a framework for the assessment of different double exposure techniques is laid out. Both the simulation environment and the utilized models, derived from well-established resist models, are discussed. Numerous simulation results are evaluated to investigate strengths and weaknesses of different double exposure approaches. Non-linear superposition techniques are examined in respect of their process performance for both standard and sub 0.25 ktief1 values. In addition to a study of these effects in the scope of basic layouts, an application to interference-assisted lithography (IAL) is proposed and discussed

In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing. 5, 11, 14However, there exist pattern configurations for which pattern features separated by less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that incorporates integer linear programming (ILP), phase conflict detection (PCD), and node-deletion bipartization (NDB) methods. We evaluate our approach on both real-world and artificially generated testcases in 45nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout. While we have previously reported other facets of our research on DPL pattern decomposition, 6 the present paper differs from that work in the following key respects: (1) instead of detecting conflict cycles and splitting nodes in conflict cycles to achieve graph bipartization, 6 we split all nodes of the conflict graph at all feasible dividing points and then formulate a problem of bipartization by ILP, PCD 8 and NDB 9 methods; and (2) instead of reporting unresolvable conflict cycles, we report the number of deleted conflict edges to more accurately capture the needed design changes in the experimental results.

Imaging contact holes has become a major technology barrier for optical lithography in the deep subwavelength era. Using hyper-numerical aperture, extreme off-axis illumination with TE-polarization, weak PSM and negative-acting resists 50nm contacts on a 90nm pitch can be produced with better than 0.3 micron depth-of-focus with 5% exposure latitude and maximum exposure latitude of greater than 15% at best focus. Large depth-of-focus across-pitch range solutions for 50nm contacts require the use of multiple exposures using unique sources but smaller focus budgets can be reduced to single exposure. This work defines possible integrated imaging systems that will allow imaging of deep sub-wavelength sized contact holes and then compares these to other solutions that have been proposed in the literature. Specifically, source design through normalized-image-log-slope, normalized-resist-image-log-slope and process window mapping, development of contact hole primitives using full mask transform correction (where the mask pattern shape, material and topography are taken into account) and resist requirements will be discussed for developing dense, mid-range and isolated pitch contact hole imaging solutions for the 45nm technology node. IntroductionStarting with the 130nm technology node, resolving contact holes is the primary feature size and pitch limiter. Relative to lines and spaces the normalized-image-log-slope (NILS) and intensity maximum of the projected image are significantly worse for contacts imaged in positive-tone resists. Our work shows NILS of less than 1.5 is typical for 160nm pitches imaged with 0.75 NA 193nm and c-Quasar. This is due in large part to the loss in cross term diffraction information that is filtered by the pupil reducing both contrast and intensity and that is then compensated by increasing the size of the contact and sampling the low NILS region near the intensity maximum to attain sizing through underexposure. It is also due to the type of off-axis illumination scheme used to attain the small pitch. Using an off-axis illuminator poles placed at the 45 degree position relative to the optical axis limits resolution to a pitch factor of 1/√2 whereas with the poles oriented on the optical axis resolution can extend to 1/2. However, while increasing resolution, this is done at a loss to contrast due to two poles being ideally oriented to form good diffraction information for each x-orientation or y-orientation feature edge while the other two are not. 1 This problem can be mitigated by using y-polarization for x-edge and x-polarization for each y-edge in a dual dipole exposure or by using azimuthally polarized source in a single exposure. 2 Yet after doing this, the lithographer is still faced with the problems inherent with underexposing low contrast images, poor process latitude and a greater propensity for line-edge-roughness in positive resist.

There are many variables that can affect lithographic dependent device yield. Because of this, it is not enough to make optical proximity corrections (OPC) based on the mask type, wavelength, lens, illumination-type and coherence. Resist chemistry and physics along with substrate, exposure, and all post-exposure processing must be considered too. Only a holistic approach to finding imaging solutions will accelerate yield and maximize performance. Since experiments are too costly in both time and money, accomplishing this takes massive amounts of accurate simulation capability. Our solution is to create a workbench that has a set of advanced user applications that utilize best-in-class simulator engines for solving litho-related DFM problems using distributive computing. Our product, ProLE™ (Programmable Lithography Engine), is an integrated system that combines Petersen Advanced Lithography Inc.'s (PAL's) proprietary applications and cluster management software wrapped around commercial software engines, along with optional commercial hardware and software. It uses the most rigorous lithography simulation engines to solve deep sub-wavelength imaging problems accurately and at speeds that are several orders of magnitude faster than current methods. Specifically, ProLE uses full vector thin-mask aerial image models or when needed, full across source 3D electromagnetic field simulation to make accurate aerial image predictions along with calibrated resist models;. The ProLE workstation from Petersen Advanced Lithography, Inc., is the first commercial product that makes it possible to do these intensive calculations at a fraction of a time previously available thus significantly reducing time to market for advance technology devices.In this work, ProLE is introduced, through model comparison to show why vector imaging and rigorous resist models work better than other less rigorous models, then some applications of that use our distributive computing solution are shown. Topics covered describe why ProLE solutions are needed from an economic and technical aspect, a high level discussion of how the distributive system works, speed benchmarking, and finally, a brief survey of applications including advanced aberrations for lens sensitivity and flare studies, opticalproximity-correction for a bitcell and an application that will allow evaluation of the potential of a design to have systematic failures during fabrication.Keywords: lithography, simulation, EDA, TCAD, RET, yield, systematic failure, DFM, PSM, GRID computing IntroductionThe ability of IC designers to simply send a completed layout to a fab and expect high production yields ended with the advent of the sub-wavelength era. As designs reached 130nm feature size and below, design and manufacturing complexity dramatically increased: the addition of non-printing features such as optical proximity correction (OPC) and phase shifters required new levels of simulation to insure functionality and yields. The gap between circuit layout and actual results on sil...