32nm gate-first high-k/metal-gate technology for high performance low power applications

Diaz, C.H.; Gotō, Kenichi; Huang, Huan-Tsung; Yasuda, Y.; Tsao, C.P.; Chu, T.T.; Lu, Wenjuan; Chang, V.S.; Hou, Yunfei; Chao, Yung-Ching; Hsu, P.F.; Chen, C.L.; Lin, Ku-Feng; Ng, Jin Aun; Wei, Yang; Chen, C.H.; Peng, Yung-Chow; Chen, C.J.; Chen, C.C.; Yu, Miao; Yeh, Lingyen; You, Kae-Dyi; Chen, K.S.; Thei, Kong–Beng; Lee, C.H.; Yang, Shixuan; Cheng, J.Y.; Huang, Kevin; Liaw, J.J.; Ku, Yao-Ching; Jang, S. M.; Chuang, Harry; Liang, Mong–Song

doi:10.1109/iedm.2008.4796770

Cited by 27 publications

(14 citation statements)

References 6 publications

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“…High-κ / metal-gate (HK / MG) stacks will be incorporated in these generations as standard technique because of their more optimal power and performance compared to SiON / Poly-Si gate stack [4,5]. Study on the reliability of HK / MG gate stacks has made progress in recent years.…”

Section: Introductionmentioning

confidence: 99%

Impact of HK / MG stacks and future device scaling on RTN

Tega

Miki

Ren³

et al. 2011

2011 International Reliability Physics Symposium

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This work demonstrates the close relationship between device scaling and the threshold voltage variation (ΔV th ) of random telegraph noise (RTN) in high-κ and metal gate (HK / MG) stacks. Statistical analysis clarifies that high temperature forming gas annealing can suppress the RTN ΔV th . And properly annealed HK FETs have smaller RTN ΔV th than SiON FETs, due mostly to fewer traps and partly to thinner inversion thickness in HK / MG stacks. Consequently, the influence of RTN on HK / MG gate stacks is less than that of random dopant fluctuation in the 22 nm generation. However, RTN may pose a difficult challenge for the 15 nm generation. In addition to the scaling dependence, we also find that characterizing hysteretic RTN behaviors due to RTN dependence on bias is essential to determine whether the observed RTN has an impact on SRAM operation or not.

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Section: Introductionmentioning

confidence: 99%

Impact of HK / MG stacks and future device scaling on RTN

Tega

Miki

Ren³

et al. 2011

2011 International Reliability Physics Symposium

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“…As an example, the SRAM cell static noise margin (SNM) trend in Fig. 5 illustrates that a 22nm HK/MG device may still have adequate SNM [1,6,[8][9][11][12]. PTM HK/MG SNM is below the average of published data at 22nm node.…”

Section: IImentioning

confidence: 97%

“…A predictive model for simple BEOL structures was presented in [4]. As shown in Table 1 [6,[8][9], more complicated BEOL structures and physical effects, such as high-k cap layer, etch damage layer, and metal grain scattering effects are existed in advanced process nodes [1]. We have developed a new capacitance model that incorporates these advanced features [10].…”

Section: IImentioning

confidence: 99%

Pathfinding for 22nm CMOS designs using Predictive Technology Models

Zhao

Cao

et al. 2009

2009 IEEE Custom Integrated Circuits Conference

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Traditional IC scaling is becoming increasingly difficult at the 22nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess the performance impact of future key modules. In this paper we propose a strategy that enables simultaneous investigation of advanced process and design concepts. Based on a customized predictive methodology and silicon data at 90-45nm nodes, compact transistor and interconnect models are developed for the next generation CMOS technology. We capture the heuristic device behavior during the scaling, which helps us to gain key insights that allow us to make tradeoffs of circuit performance metrics for next technology node. I.INTRODUCTION CMOS technology scaling is increasingly challenged by physics and manufacturing limits at 22nm and beyond [1]. These challenges reduce the predictability of circuit performance and increase the development cycle for new IC products. Continued CMOS scaling, it requires comprehending the technology impacts and capabilities as early as possible. This enables identification of potential issues, allows adaptive design decisions up front, and guarantees managing the time to market. Objecting such early stage exploration requires Predictive Technology Models (PTM) to assess performance trends, evaluate key modules before Silicon is ready, and facilitates the development of future CMOS technology [2][3].This work proposes such a predictive strategy to enable simultaneous exploration of low power CMOS process and design concepts. We incorporate the general PTM methodology [2][3][4], with customized enhancements of transistor-level and interconnect-level physical effects [1]. These customized PTM models are systematically calibrated to 90-45nm Poly/SiON silicon data and published high-k/metal gate (HK/MG) information. Section II briefly presents the predictive methodology. We leverage these predictive models to quantify projections of various behaviors of CMOS devices, interconnect, and representative design modules, such as ring oscillator (RO), standard cell and SRAM for the 22nm node. The results reveal the trends, potential, and limits of technology scaling, and provide important guidance and insight into process and design choices (Section III).

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“…Layout dimensions for 22nm (25nm drawn gate length) 6-T SRAM cells were selected based on recent publications [6][7][8][9][10] and are summarized in Table I for a conventional notched cell layout. The quasi-planar bulk MOSFET design was optimized via 3-D device simulations to achieve the highest I ON for I OFF = 3nA/um, at V dd = 1V: electrical channel length (distance between the points where the source/drain doping profiles fall to 2×10 19 cm -3 ) L eff = 27nm; effective oxide thickness EOT = 9Å; source/drain extension junction depth X J,ext = 10nm.…”

Section: Nm Bulk Sram Cell Design Studymentioning

confidence: 99%

Tri-gate bulk CMOS technology for improved SRAM scalability

Shin

Nikolić

Liu

et al. 2010

2010 Proceedings of the European Solid State Device Research Conference

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-A simple approach for manufacturing quasi-planar tri-gate bulk MOSFET structures is demonstrated and shown to be effective for reducing variation in 6T-SRAM read and write margins, in an early 28nm CMOS technology. With optimization of the pocket implant doses, quasi-planar bulk CMOS technology can facilitate voltage scaling. It also provides a means to achieve high yield with a notch-less 6T-SRAM cell layout, to facilitate area scaling. I. INTRODUCTIONA challenge for continued SRAM scaling is threshold voltage (V T ) mismatch due to process-induced variations [1], which degrades the minimum operating voltage (V min ) of an SRAM array [2]. To address this challenge, an improved transistor design that provides for reduced short-channel effects (i.e., improved gate control over the channel potential) is required. The quasi-planar tri-gate bulk MOSFET [3] is an example of such a design; it utilizes a gate electrode that is physically wrapped around the top portion of the channel region to provide for greater capacitive coupling between the gate and the channel region [4]. In this work, a timed etch in dilute hydrofluoric (HF) acid solution is used to recess the isolation oxide prior to gate-stack formation, to form quasiplanar bulk MOSFETs using an otherwise conventional fabrication process flow.Improvements in transistor performance and SRAM yield are demonstrated in an early 28nm CMOS technology. The benefits of quasi-planar bulk MOSFET technology for voltage and area scaling are then assessed using three-dimensional (3-D) device simulations with atomistic doping profiles and analytical modeling to estimate 6T-SRAM cell yield for 22nm CMOS technology.

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32nm gate-first high-k/metal-gate technology for high performance low power applications

Cited by 27 publications

References 6 publications

Impact of HK / MG stacks and future device scaling on RTN

Impact of HK / MG stacks and future device scaling on RTN

Pathfinding for 22nm CMOS designs using Predictive Technology Models

Tri-gate bulk CMOS technology for improved SRAM scalability

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