33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models

Wan, Weier; Kubendran, Rajkumar; Eryilmaz, Şükrü Burç; Zhang, Wenqiang; Liao, Yehong; Wu, Dehai; Deiss, Stephen; Gao, Bin; Raina, Priyanka; Joshi, Siddharth; Wu, Huaqiang; Cauwenberghs, Gert; Wong, H.-S. Philip

doi:10.1109/isscc19947.2020.9062979

Cited by 108 publications

(54 citation statements)

References 4 publications

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“…Memristive crosspoint has been shown able to accelerate different problems based on MVM, such as the training [16,27,38] and inference [20,41] of neural networks, image processing [18], sparse coding [29], optimization problems [6,24] and the solution of linear equations through iterative numerical approaches [14,43]. Integrated circuits comprising memristive arrays and the circuitry need to generate the input, such as digital-analog-converters (DAC), sense and read the outputs, such as transimpedance amplifiers (TIA) and analog-digital-converters (ADC), and cell selecting and routing, able to accelerate MVM have been proposed [5,37,42], outperforming modern processor both in throughput and energy saving [42].…”

Section: In-memory Matrix-vector-multiplication Acceleratormentioning

confidence: 99%

One Step in-Memory Solution of Inverse Algebraic Problems

Pedretti

2021

Special Topics in Information Technology

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Machine learning requires to process large amount of irregular data and extract meaningful information. Von-Neumann architecture is being challenged by such computation, in fact a physical separation between memory and processing unit limits the maximum speed in analyzing lots of data and the majority of time and energy are spent to make information travel from memory to the processor and back. In-memory computing executes operations directly within the memory without any information travelling. In particular, thanks to emerging memory technologies such as memristors, it is possible to program arbitrary real numbers directly in a single memory device in an analog fashion and at the array level, execute algebraic operation in-memory and in one step. In this chapter the latest results in accelerating inverse operation, such as the solution of linear systems, in-memory and in a single computational cycle will be presented.

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Section: In-memory Matrix-vector-multiplication Acceleratormentioning

confidence: 99%

One Step in-Memory Solution of Inverse Algebraic Problems

Pedretti

2021

Special Topics in Information Technology

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“…The chip operates at 1.8V supply for both digital and analog blocks. Measurements show each neuron operation with 63 nW static power drawn from a 1.8 V supply [9]. The total power (static+dynamic) consumption of the chip (256 I&F neurons, biasing and peripherals) is 140.6 µW for data throughput of 92.5 MSpikes/s.…”

Section: System-on-chip Architecture and Implementationmentioning

confidence: 99%

“…The neuron design supports a variety of activation functions, that can cater to deep learning and neuromorphic applications. At only a fraction of the energy efficiency compared to the state-of-the-art implementations, this architecture can be easily adopted and scaled for large networks [9].…”

Section: Introductionmentioning

confidence: 99%

“…Correlated double sampling (CDS) provides periodic offset cancellation, mitigating systematic variations in the circuit and also establishes a DC operating point for the capacitively coupled OTA. A detailed schematic and timing waveform for the 16×16 I&F neuron circuit are given in [9], where the neurons were configured to implement step and sigmoid activation with binary output. This work extends the reconfigurability of the neuron, to implement ReLU and logistic sigmoid activation with binary or ternary output.…”

Section: Introductionmentioning

confidence: 99%

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A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver

Kubendran

Wan

Joshi

et al. 2020

International Conference on Neuromorphic Systems 2020

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An ultra-low power integrate-and-fire neuron array transceiver with a multi-modal neuron architecture is presented. The design features an array of 16×16 charge-mode mixed-signal neurons that can be configured to implement a variety of activation functions, including step, sigmoid and Rectified Linear Unit (ReLU), through reconfiguration of clocking waveforms through partial reset in charge accumulation and additive stochastic noise by Linear Feedback Shift Register (LFSR) coupling. The neuron outputs spike-based sparse synchronous events, which are either binary (event/no event) or ternary (positive/negative/no events). The reconfigurable energyefficient design makes this architecture suitable for deep learning and neuromorphic applications like Restricted Boltzmann Machines, Convolutional Neural Networks and general event-driven computing. The 1.796 mm 2 chip fabricated in 130nm CMOS technology consumes 140.6 µW from a 1.8V supply at 92.5 MSpikes/s achieving an energy efficiency Figure-of-Merit (FoM) of 1.52 pJ/Spike. A CNN architecture implemented on the chip using sigmoid and ReLU activation achieves MNIST prediction accuracy of 94.8% and 96.9%.

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“…The realization of activation and intra-layer communication is carried out by off-chip field-programmed gate array (FPGA). Recently, this field has been rapidly developing toward monolithically integrated memristive neuromorphic systems, even though the memristive analog behavior has not been fully exploited ( Liu et al, 2020 ; Wan et al, 2020 ).…”

Section: Introductionmentioning

confidence: 99%

Integration and Co-design of Memristive Devices and Algorithms for Artificial Intelligence

et al. 2020

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Summary Memristive devices share remarkable similarities to biological synapses, dendrites, and neurons at both the physical mechanism level and unit functionality level, making the memristive approach to neuromorphic computing a promising technology for future artificial intelligence. However, these similarities do not directly transfer to the success of efficient computation without device and algorithm co-designs and optimizations. Contemporary deep learning algorithms demand the memristive artificial synapses to ideally possess analog weighting and linear weight-update behavior, requiring substantial device-level and circuit-level optimization. Such co-design and optimization have been the main focus of memristive neuromorphic engineering, which often abandons the “non-ideal” behaviors of memristive devices, although many of them resemble what have been observed in biological components. Novel brain-inspired algorithms are being proposed to utilize such behaviors as unique features to further enhance the efficiency and intelligence of neuromorphic computing, which calls for collaborations among electrical engineers, computing scientists, and neuroscientists.

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33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models

Cited by 108 publications

References 4 publications

One Step in-Memory Solution of Inverse Algebraic Problems

One Step in-Memory Solution of Inverse Algebraic Problems

A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver

Integration and Co-design of Memristive Devices and Algorithms for Artificial Intelligence

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