2019 IEEE Asian Solid-State Circuits Conference (A-Sscc) 2019
DOI: 10.1109/a-sscc47793.2019.9056951
|View full text |Cite
|
Sign up to set email alerts
|

33us, 94uJ Optimal Ate Pairing Engine on BN Curve over 254b Prime Field in 65nm CMOS FDSOI

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
18
0

Year Published

2021
2021
2023
2023

Publication Types

Select...
3
2

Relationship

1
4

Authors

Journals

citations
Cited by 7 publications
(18 citation statements)
references
References 7 publications
0
18
0
Order By: Relevance
“…We profiled various CIOS multipliers on our test chip and verified that energy consumption saturates at 64b word size, with 50% and 25% lower energy than conventional 16b and 32b architectures respectively. It is also more energy-efficient than previous work [2,3,4] when normalized with respect to prime size. A pair of cascaded 381b adder-subtractors is used for modular addition and subtraction, while modular inversion is implemented using exponentiation following Fermat's theorem.…”
mentioning
confidence: 84%
See 2 more Smart Citations
“…We profiled various CIOS multipliers on our test chip and verified that energy consumption saturates at 64b word size, with 50% and 25% lower energy than conventional 16b and 32b architectures respectively. It is also more energy-efficient than previous work [2,3,4] when normalized with respect to prime size. A pair of cascaded 381b adder-subtractors is used for modular addition and subtraction, while modular inversion is implemented using exponentiation following Fermat's theorem.…”
mentioning
confidence: 84%
“…3 shows our design of an energy-efficient modular arithmetic unit for the BLS12-381 curve. Modular arithmetic in Montgomery domain is standard for such large prime fields, and previous work on pairing accelerators use either high-performance parallel pipelined architectures with large area overhead [3,4] or compact serial multipliers with lower energy-efficiency [2]. To balance area and energy-efficiency, we implement Montgomery modular multiplication using the coarsely integrated operand scanning (CIOS) approach [5], which splits zero-padded inputs into six 64b words and operates on them iteratively using a 64b × 64b multiplier and a 128b + 64b + 64b adder, both utilizing carry-save structures for shorter critical path delay.…”
mentioning
confidence: 99%
See 1 more Smart Citation
“…2, contains arithmetic unit that realizes Montgomery multiplication, and the 2nd-layer sequencer that specifies the detailed arithmetic order. Three 1st-layer sequences are attached to three calculation cores, and units are fully pipelined F p 2 multiplier, constant multiplier, and ξ multiplier proposed by Ikeda et al [6].…”
Section: Proposed Architecturementioning
confidence: 99%
“…Awano [5] optimized F p 12 calculation by global optimization of pipelined F p 2 multipliers, results in 9,270 cycles. Ikeda [6] optimized number of…”
Section: Introductionmentioning
confidence: 99%